• Journal of information and communication convergence engineering
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• v.12 no.1
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• pp.46-52
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• 2014

This article presents key research needs in three-dimensional integrated circuit (3D IC) architectural floorplanning. Architectural floorplaning is done at a very early stage of 3D IC design process, where the goal is to quickly evaluate architectural designs described in register-transfer level (RTL) in terms of power, performance, and reliability. This evaluation is then fed back to architects for further improvement and/or modifications needed to meet the target constraints. We discuss the details of the following research needs in this article: block-level modeling, through-silicon-via (TSV) insertion and management, and chip/package co-evaluation. The goal of block-level modeling is to obtain physical, power, performance, and reliability information of architectural blocks. We then assemble the blocks into multiple tiers while connecting them using TSVs that are placed in between hard IPs and inside soft IPs. Once a full-stack 3D floorplanning is obtained, we evaluate it so that the feedback is provided back to architects.

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.45-49
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• 2022

Through Silicon Via (TSV) is a technology that interconnects chips through silicon vias. TSV technology can achieve shorter distance compared to wire bonding technology with excellent electrical characteristics. Due to this characteristic, it is currently being used in many fields that needs faster communication speed such as memory field. However, there is performance degradation issue on TSV technology due to the parasitic capacitance. To deal with this problem, in this study, the parasitic capacitance with TSV design factors is analyzed using commercial tool. TSV design factors were set in three categories: size, aspect ratio, pitch. Each factor was set by dividing the range with TSV used for memory and package. Ansys electronics desktop 2021 R2.2 Q3D was used for the simulation to acquire parasitic capacitance data. DOE analysis was performed based on the reaction surface method. As a result of the simulation, the most affected factors by the parasitic capacitance appeared in the order of size, pitch and aspect ratio. In the case of memory, each element interacted, and in the case of package, it was confirmed that size * pitch and size * aspect ratio interact, but pitch * aspect ratio does not interact.

• Journal of electromagnetic engineering and science
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• v.11 no.4
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• pp.282-289
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• 2011

GHz electromagnetic interference (EMI) characteristics are analyzed for a 3dimensional (3D) stacked chip power distribution network (PDN) with through silicon via (TSV) connections. The EMI problem is mostly raised by P/G (power/ground) noise due to high switching current magnitudes and high PDN impedances. The 3D stacked chip PDN is decomposed into P/G TSVs and vertically stacked capacitive chip PDNs. The TSV inductances combine with the chip PDN capacitances produce resonances and increase the PDN impedance level in the GHz frequency range. These effects depend on stacking configurations and P/G TSV designs and are analyzed using the P/G TSV model and chip PDN model. When a small size chip PDN and a large size chip PDN are stacked, the small one's impedance is more seriously affected by TSV effects and shows higher levels. As a P/G TSV location is moved to a corner of the chip PDNs, larger PDN impedances appear. When P/G TSV numbers are enlarged, the TSV effects push the resonances to a higher frequency range. As a small size chip PDN is located closer to the center of a large size chip PDN, the TSV effects are enhanced.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2008.11a
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• pp.18-18
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• 2008

3차원 패키징 System In Package (SIP)구조에서 Chip to Chip 단위 Interconnection 역할을 하는 Through Silicon Via(TSV)를 형성하기 위하여 Pulsating RF bias가 장착된 Inductively Coupled Plasma Etcher 장비를 이용하였다. 이 Pulsating 플라즈마 공정 방법은 주기적인 펄스($50{\sim}500Hz$)와 듀티($20{\sim}99%$) cycle 조절이 가능하며, 플라즈마 에칭특성에 영향을 주는 플라즈마즈마 발생 On/Off타임을 조절할 수 있다. 예를 들면, 플라즈마 발생 Off일 경우에는 이온(SFx+, O+)과 래디컬(SF*, F*, O*)의 농도 및 활성도를 급격하게 줄이는 효과를 얻을 수가 있는데, 이러한 효과는 식각 에칭시, 이온폭격의 손상을 급격하게 줄일 수 있으며, 실리콘 표면과 래디컬의 화학적 반응을 조절하여 에칭 측벽 식각 보호막 (SiOxFy : Silicon- Oxy- Fluoride)을 형성하는데 영향을 미친다. 그리고, TSV 형성에 있어서 큰 문제점으로 지적되고 있는 언더컷과 수평에칭 (Horizontal etching)을 개선하기 위한 방법으로, Black-Siphenomenon을 이번 실험에 적용하였다. 이 Black-Si phenomenon은 Bare Si샘플을 이용하여, 언더컷(Undercut) 및 수평 에칭 (Horizontal etching)이 최소화 되는 공정 조건을 간편하게 평가 할 수 있는 방법으로써, 에칭 조건 및 비율을 최적화하는 데 효율적이었다. 결과적으로, Pulsating RF bias가 장착된 Inductively Coupled Plasma Etcher 장비를 이용한 에칭실험은 펄스 주파수($50{\sim}500Hz$)와 듀티($20{\sim}99%$) cycle 조절이 가능하여, 이온(SFx+, O+)과 래디컬(SF*, F*, O*)의 농도와 활성화를 조절 하는데 효과적이었으며, Through Silicon Via (TSV)를 형성 하는데 있어서 Black-Si phenomenon 적용은 기존의 Continuous 플라즈마 식각 결과보다 향상된 에칭 조건 및 에칭 프로파일 결과를 얻는데 효과적이었다.

• ETRI Journal
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• v.36 no.2
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• pp.301-308
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• 2014

Three-dimensional integration technology results in area savings, platform power savings, and an increase in performance. Through-silicon via (TSV) assembly and manufacturing processes can potentially introduce defects. This may result in increases in manufacturing and test costs and will cause a yield problem. To improve the yield, spare TSVs can be included to repair defective TSVs. This paper proposes a new built-in self-test feature to identify defective TSV channels. For defective TSVs, this paper also introduces dynamic self-repair architectures using code-based and hardware-mapping based repair.

• Korean Journal of Metals and Materials
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• v.48 no.11
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• pp.1028-1034
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• 2010

In the development of 3D package, through silicon via (TSV) formation technology by using deep reactive ion etching (DRIE) is one of the key processes. We performed the Bosch process, which consists of sequentially alternating the etch and passivation steps using $SF_6$ with $O_2$ and $C_4F_8$ plasma, respectively. We investigated the effect of changing variables on vias: the gas flow time, the ratio of $O_2$ gas, source and bias power, and process time. Each parameter plays a critical role in obtaining a specified via profile. Analysis of via profiles shows that the gas flow time is the most critical process parameter. A high source power accelerated more etchant species fluorine ions toward the silicon wafer and improved their directionality. With $O_2$ gas addition, there is an optimized condition to form the desired vertical interconnection. Overall, the etching rate decreased when the process time was longer.

• ETRI Journal
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• v.34 no.5
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• pp.706-712
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• 2012

In previous work, novel maskless bumping and no-flow underfill technologies for three-dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low-volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no-flow underfill material named "fluxing underfill" is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two-tier stacked TSV chips are sucessfully stacked.

• Journal of Welding and Joining
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• v.31 no.6
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• pp.77-83
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• 2013

3D packaging technology using TSV (Through Silicon Via)has been studied in the recent years to achieve higher performance, lower power consumption and smaller package size because electrical line is shorter electrical resistivity than any other packaging technology. To stack TSV chips vertically, reliable and robust bonding technology is required because mechanical stress and thermal stress cause fracture during the bonding process. Cu pillar/solder ${\mu}$-bump bonding process is usually to interconnect TSV chips vertically although it has weak shape to mechanical stress and thermal stress. In this study, we suggest Insert-Bump (ISB) bonding process newly to stack TSV chips. Through experiments, we tried to find optimal bonding conditions such as bonding temperature and bonding pressure. After ISB bonding, we observed microstructure of bump joint by SEM and then evaluated properties of bump joint by die shear test.

• Journal of Welding and Joining
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• v.31 no.3
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• pp.11-16
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• 2013

Through-silicon-via (TSV) is a major technology in microelectronics for three dimensional high density packaging. The 3-dimensional TSV technology is applied to CMOS sensors, MEMS, HB-LED modules, stacked memories, power and analog, SIP and so on which can be employed to car electronics. The copper electroplating is widely used in the TSV filling process. In this paper, the various Cu filling methods using the control of the plating process were described in detail including recent studies. Via filling behavior by each method was also introduced.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.05a
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• pp.669-670
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• 2010