Journal of Welding and Joining

The Korean Welding and Joining Society (대한용접접합학회)
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Various Cu Filling Methods of TSV for Three Dimensional Packaging

3차원 패키징을 위한 TSV의 다양한 Cu 충전 기술

  • Roh, Myong-Hoon (Department of Materials Science and Engineering, University of Seoul) ;
  • Lee, Jun-Hyeong (Department of Materials Science and Engineering, University of Seoul) ;
  • Kim, Wonjoong (Department of Materials Science and Engineering, University of Seoul) ;
  • Jung, Jae Pil (Department of Materials Science and Engineering, University of Seoul) ;
  • Kim, Hyeong-Tea (APRO R&D)
  • 노명훈 (서울시립대학교 공과대학 신소재공학과) ;
  • 이준형 (서울시립대학교 공과대학 신소재공학과) ;
  • 김원중 (서울시립대학교 공과대학 신소재공학과) ;
  • 정재필 (서울시립대학교 공과대학 신소재공학과) ;
  • 김형태 ((주)아프로 알앤디)
  • Published : 2013.06.30
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Abstract

Through-silicon-via (TSV) is a major technology in microelectronics for three dimensional high density packaging. The 3-dimensional TSV technology is applied to CMOS sensors, MEMS, HB-LED modules, stacked memories, power and analog, SIP and so on which can be employed to car electronics. The copper electroplating is widely used in the TSV filling process. In this paper, the various Cu filling methods using the control of the plating process were described in detail including recent studies. Via filling behavior by each method was also introduced.

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References

  1. M. Motoyoshi : Through-silicon via (TSV), Proceedings of IEEE, 97-1 (2009), 43-48 https://doi.org/10.1109/JPROC.2008.2007462
  2. X. Zhang, T.C. Chai, J.H. Lau, C.S. Selvanayagam, K. Biswas, S. Liu, D. Pinjala, (...), C.J. Vath III : Development of through silicon via (TSV) interposer techonology for large die (21x21mm) fine-pitch Cu/low-k FCBGA package, Proceedings-Electronic Components and Technology Conference, (2009), 305-312
  3. J.A.T. Norman, M. Perez, S.E. Schulz, T. Waechtler : New precursors for CVD copper metallization, Microelectron. Eng., 85-100 (2008) 2159-2163 https://doi.org/10.1016/j.mee.2008.05.036
  4. M.J. Wolf, T. Dretschkow, B. Wunderle, N. Jurgensen, G. Engelmann, O. Ehrmann, A. Uhlig, (...), H. Reichl : High aspect ratio TSV copper filling with different seed layers, Proceedings-Electronic Components and Technology Conference, (2008) 563-570
  5. T.C. Tsai, W.C. Tsao, W. Lin, C.L. Hsu, C.L. Lin, C.M. Hsu, J.F. Lin, C.C. Huang, J.Y. Wu, CMP process development for the via-middle 3D TSV applications at 28nm technology node, Microelectronic Engineering, 92 (2012) 29-33 https://doi.org/10.1016/j.mee.2011.03.004
  6. S.J. Hong, J.H. Jung, J.P. Jung, M. Mayer, Y.N. Zhou : Sn bumping without photoresist mould and Si dice stacking for 3-D packaging, IEEE Transactions on Advanced Packaging, 33-4 (2010), 912-917 https://doi.org/10.1109/TADVP.2010.2049019
  7. S.C. Hong, W.G. Lee, J.K. Park, W.J. Kim, and J.P. Kim : Cu filling into TSV and non-PR Sn bumping for 3 dimension chip packaging, Journal of KWJS, 29-1 (2011) 9-13 (in Korean) https://doi.org/10.5781/KWJS.2011.29.1.009
  8. S.H. Choa and C.G. Song : Thermo-mechanical reliability analysis of copper TSV, Journal of KWJS, 29-1 (2011) 46-51 (in Korean) https://doi.org/10.5781/KWJS.2011.29.1.046
  9. H. Y. Li, E. Liao, X. F. Pang, H. Yu, X. X. Yu, J. Y. Sun, "Fast Electroplating TSV Process Development for the Via-Last Approach", 2010 Electronic Components and Technology Conference, (2010), 777-780
  10. D. Malta, C. Gregory, D. Temple, T. Knutson, C. Wang, T. Richardson, Y. Zhang, R. Rhoades : Integrated process for defect-free copper plating and chemical-mechanical polishing of through-silicon vias for 3D interconnects, Proceedings-Electronic Components and Technology Conference (2010), 1769-1775
  11. K.Y.K. Tsui, S.K. Yau, V.C.K. Leung, P. Sun, D.X.Q. Shi : Parametric Study of Electroplatingbased Via-filling Process for TSV Applications, Int'l Conf. on Electron. Pack. Tech & High Dens. Pack. (ICEPT-HDP), (2009), 23-27
  12. T. Kenji, T. Hiroshi, T. Yoshihiro, Y. Yasuhiro, H. Masataka, S. Tomotoshi, M. Tadahiro, S. Masahiro, B. Manabu : Current status of research and development for three-dimensional chip stack technology, J. Appl. Phys. 40 (2001), 3032-3037 https://doi.org/10.1143/JJAP.40.3032
  13. S.W.R. Lee, R. Ho, S.X.D. Zhang, C. K. Wong : 3D stacked flip chip packaging with through silicon vias and copper plating or conductive adhesive filling, Proceed. Elec. Pack. Tech. Conf., (2005) 795-801
  14. B.H. Kim, H.C. Kim, K.J. Chun, J.H. KI, Y.S. Tak : Cantilevert-type microelectromechanical systems probe card with throuhg-wafer interconnects for fine pitch and high-speed testing, Jpn. J. Applied Physics 43(6B) (2004) 3877 https://doi.org/10.1143/JJAP.43.3877
  15. E.H. Choi, Y.S. Lee, and S.K. Rha : Effects of current density and organic additives on via copper electroplating for 3D packaging, Kor. J. Mater Res., 22-7 (2012), 374-378 https://doi.org/10.3740/MRSK.2012.22.7.374
  16. C. Fang, A.L. Corre, and D. Yon : Copper electroplating into deep microvias for the "SiP" application, Microelectronic Engineering 88 (2011), 749-753 https://doi.org/10.1016/j.mee.2010.07.034
  17. R. Beica, C. Sharbono, and T. Ritzdorf : Through silicon via copper electrodeposition for 3D integration, Electronic components and technology conference, IEEE (2008), 577-583
  18. L. Hofmann, R. Ecke, S.D. Schulz, and T. Gessner : Investigations regarding Through Silicon Via filling for 3D integration by Periodic Pulse Reverse plating with and without additives, Microelectronic Engineering 88 (2011), 705-708 https://doi.org/10.1016/j.mee.2010.06.040
  19. S.C. Hong, W.G. Lee, W.J. Kim, J.H. Kim, and J.P. Jung : Reduction of defects in TSV filled with Cu by high-speed 3-step PPR for 3D Si chip stacking, Microelectronics Reliability, 51 (2011) 2228-2235 https://doi.org/10.1016/j.microrel.2011.06.031
  20. Q. Li, H. Ling, H. Cao, Z. Bian, M. Li, and D. Mao : Through silicon via filling by copper electroplating in acidic cupric methanesulfonate bath, International conference on electronic packaging technology & High density packaging (ICEPT-HDP), IEEE, (2009), 68-72
  21. T.H. Tsai and J.H. Juang : Electrochemical investigations for copper electrodeposition of throughsilicon via, Microelectronic Engineering 88 (2011), 195-199 https://doi.org/10.1016/j.mee.2010.10.018