• 제목/요약/키워드: TSUPREM4

검색결과 24건 처리시간 0.03초

A Study on Lateral Distribution of Implanted Ions in Silicon

  • Jung, Won-Chae;Kim, Hyung-Min
    • Transactions on Electrical and Electronic Materials
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    • 제7권4호
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    • pp.173-179
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    • 2006
  • Due to the limitations of the channel length, the lateral spread for two-dimensional impurity distributions is critical for the analysis of devices including the integrated complementary metal oxide semiconductor (CMOS) circuits and high frequency semiconductor devices. The developed codes were then compared with the two-dimensional implanted profiles measured by transmission electron microscope (TEM) as well as simulated by a commercial TSUPREM4 for verification purposes. The measured two-dimensional TEM data obtained by chemical etching-method was consistent with the results of the developed analytical model, and it seemed to be more accurate than the results attained by a commercial TSUPREM4. The developed codes can be applied on a wider energy range $(1KeV{\sim}30MeV)$ than a commercial TSUPREM4 of which the maximum energy range cannot exceed 1MeV for the limited doping elements. Moreover, it is not only limited to diffusion process but also can be applied to implantation due to the sloped and nano scale structure of the mask.

강유전체 PZT박막을 이용한 MFMIS소자의 모델링 및 특성에 관한 시뮬레이션 연구 (Computer Modeling and characteristics of MFMIS devices Using Ferroelectric PZT Thin Film)

  • 국상호;박지온;문병무
    • 한국전기전자재료학회논문지
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    • 제13권3호
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    • pp.200-205
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    • 2000
  • This paper describes the structure modeling and operation characteristics of MFMIS(metal-ferroelectric-metal-insulator-semiconductor) device using the Tsuprem4 which is a semiconductor device tool by Avanti. MFMIS device is being studied for nonvolatile memory application at various semiconductor laboratory but it is difficult to fabricate and analyze MFMIS devices using the semiconductor simulation tool: Tsuprem4, medici and etc. So the new library and new materials parameters for adjusting ferroelectric material and platinum electrodes in the tools are studied. In this paper structural model and operation characteristics of MFMIS devices are measured, which can be easily adopted to analysis of MFMIS device for nonvolatile memory device application.

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실리콘에 $BF_2$로 이온주입후에 Boron 이온의 일차원 및 이차원적인 분포해석 (Analysis of one- and two-dimensional boron distribution in implanted $BF_2$ silicon)

  • 정원채
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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    • pp.99-100
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    • 2006
  • $BF_2$ molecule 이온주입은 ULSI기술에 있어서 ultra shallow 정합형성을 위해고 P-MOS를 제작하는데 매우 유용한 기술이다. 주입된 boron 이온의 분포를 위해서 $0.05{\mu}m$ 나노스케일의 마스크사이즈의 패턴에 이온 주입한 결과를 일차원적인 분포해석을 위해서 UT-Marlowe tool을 사용하여 gauss 및 pearson 모델의 도핑분포를 나타내었다. 또한 이 데이터를 TSUPREM4에 적용하여 이차원적인 도핑분포와 열처리 후에 boron의 gauss 및 pearson의 모델의 도핑분포를 본 논문에 나타내었다.

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[ 0.1\;μm ] SOI-MOSFET의 적정 채널도핑농도에 관한 시뮬레이션 연구 (Investigation of Optimal Channel Doping Concentration for 0.1\;μm SOI-MOSFET by Process and Device Simulation)

  • 최광수
    • 한국재료학회지
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    • 제18권5호
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    • pp.272-276
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    • 2008
  • In submicron MOSFET devices, maintaining the ratio between the channel length (L) and the channel depth (D) at 3 : 1 or larger is known to be critical in preventing deleterious short-channel effects. In this study, n-type SOI-MOSFETs with a channel length of $0.1\;{\mu}m$ and a Si film thickness (channel depth) of $0.033\;{\mu}m$ (L : D = 3 : 1) were virtually fabricated using a TSUPREM-4 process simulator. To form functioning transistors on the very thin Si film, a protective layer of $0.08\;{\mu}m$-thick surface oxide was deposited prior to the source/drain ion implantation so as to dampen the speed of the incoming As ions. The p-type boron doping concentration of the Si film, in which the device channel is formed, was used as the key variable in the process simulation. The finished devices were electrically tested with a Medici device simulator. The result showed that, for a given channel doping concentration of $1.9{\sim}2.5\;{\times}\;10^{18}\;cm^{-3}$, the threshold voltage was $0.5{\sim}0.7\;V$, and the subthreshold swing was $70{\sim}80\;mV/dec$. These value ranges are all fairly reasonable and should form a 'magic region' in which SOI-MOSFETs run optimally.

NMOSFET SOI 소자의 Current Kink Effect 감소에 관한 연구 (A Study on the Reduction of Current Kink Effect in NMOSFET SOI Device)

  • 한명석;이충근;홍신남
    • 전자공학회논문지T
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    • 제35T권2호
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    • pp.6-12
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    • 1998
  • 박막의 SOI(Silicon-On-Insulator) 소자는 짧은 채널 효과(short channel effect), subthreshold slope의 개선, 이동도 향상, latch-up 제거 등 많은 이점을 제공한다. 반면에 이 소자는 current kink effect와 같이 정상적인 소자 동작에 있어 주요한 저해 요소인 floating body effect를 나타낸다. 본 논문에서는 이러한 문제를 해결하기 위해 T-형 게이트 구조를 갖는 SOI NMOSFET를 제안하였다. T-형 게이트 구조는 일부분의 게이트 산화막 두께를 다른 부분보다 30nm 만큼 크게 하여 TSUPREM-4로 시뮬레이션 하였으며, 이것을 2D MEDICI mesh를 구성하여 I-V 특성 시뮬레이션을 시행하였다. 부분적으로 게이트 산화층의 두께가 다르기 때문에 게이트 전계도 부분적으로 차이가 발생되어 충격 이온화 전류의 크기도 줄어든다. 충격 이온화 전류가 감소한다는 것은 current kink effect가 감소하는 것을 의미하며, 이것을 MEDICI 시뮬레이션을 통해 얻어진 충격 이온화 전류 곡선, I-V 특성 곡선과 정공 전류의 분포 형태를 이용하여 제안된 구조에서 current kink effect가 감소됨을 보였다.

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경사진 게이트를 갖는 Recessed Source SOI LDMOS (An SOI LDMOS with Graded Gate and Recessed Source)

  • 김정희;최연익;정상구
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2001년도 하계학술대회 논문집 C
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    • pp.1451-1453
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    • 2001
  • An SOI(Silicon-On-Insulator) LD(Lateral Double-diffused)MOS with graded gate and recessed source is proposed. The proposed structure can increase the breakdown voltage by reducing the electric field crowding at the edge of gate. Simulation results by TSUPREM4 and MEDICI have shown that the breakdown voltage of proposed device was found to be 52 V while that of conventional device was 45 V. At the same breakdown voltage of 45 V, the on-resistance of the LDMOS with graded gate and recessed source was 14.4 % lower than that of conventional structure.

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Optimal Design of Trench Power MOSFET for Mobile Application

  • Kang, Ey Goo
    • Transactions on Electrical and Electronic Materials
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    • 제18권4호
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    • pp.195-198
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    • 2017
  • This research analyzed the electrical characteristics of an 80 V optimal trench power MOSFET (metal oxide field effect transistor) for mobile applications. The power MOSFET is a fast switching device in fields with low voltage(<100 V) such as mobile application. Moreover, the power MOSFET is a major carrier device that is not minor carrier accumulation when the device is turned off. We performed process and device simulation using TCAD tools such as MEDICI and TSUPREM. The electrical characteristics of the proposed trench gate power MOSFET such as breakdown voltage and on resistance were compared with those of the conventional power MOSFET. Consequently, we obtained breakdown voltage of 100 V and low on resistance of $130m{\Omega}$. The proposed power MOSFET will be used as a switch in batteries of mobile phones and note books.

2.5kV급 Power IGBT 소자의 설계 및 제작에 관한 연구 (A Design of 2.5kV Power IGBT for High Power)

  • 강이구;안병섭;남태진;김범준;이용훈;정헌석
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2009년도 하계학술대회 논문집
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    • pp.143-143
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    • 2009
  • 본 논문은 2500V급 planar type의 NPT(Nun-Punch Through)형 IGBT설계 및 제작에 앞서 IGBT(Insulated Gate Bipolar Transistor)소자가 갖는 구조적 변수가 전기적 특성 (Breakdown Voltage, Turnoff Time, Saturation Voltage, 등)결과에 미치는 영향을 분석하여 IGBT 소자가 갖는 구조적 손실을 최적화 하는데 목표를 두었다. 최적화의 진행은 공정 시뮬레이터인 Tsuprem4와 디바이스 분석 시뮬레이터인 MEDICI를 이용하여 소자가 갖는 각각의 parameter값이 전기적 특성에 미치는 영향을 분석함으로 진행 되어졌으며, 향후 고속철 등과 같은 대용량 산업에 기여할 것으로 판단된다.

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NMOSFET SOI 소자에서 부분적 게이트 산화막 두께 변화에 의한 돌연 전류 효과 고찰 (A Study on the Current Kink Effect in NMOSFET SOI Device with the Varying Gate Oxide Thickness)

  • 한명석;이충근홍신남
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1998년도 추계종합학술대회 논문집
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    • pp.545-548
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    • 1998
  • Thin film SOI(Silicon-On-Insulator) devices exhibit floating body effect. In this paper, SOI NMOSFET is proposed to solve this problem. Some part of gate oxide was considered to be 30nm~80nm thicker than the other normal gate oxide and simulated with TSUPREM-4. The I-V characteristics were simulated with 2D MEDICI mesh. Since part of gate oxide has different oxide thickness in proposed device, the gate electric field strength is not the same throught the gate and consequently the reduction of current kink effect is occurred.

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Deep Sub-Half Micron PMOSFETs의 DIBL 특성에 관한 연구 (A Study on DIBL Characteristics in Deep Sub-Half Micron PMOSFETs)

  • 신희갑;류찬영;이철인;서용진;김태형;장의구
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1995년도 추계학술대회 논문집
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    • pp.232-235
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    • 1995
  • To improve the DIBL characteristics of deep sub micron BC PMOSFETs, the methods of DCI(Deep Channel Implantation) and Hale Implantation have been reported. In this study, using the process simulator TSUPREM4, we simulated the 0.25$\mu\textrm{m}$ and 0.45$\mu\textrm{m}$ gate length BC PMOSFETs applying the both methods to improve the DIBL characteristics, and their electric characteristics were compared to find the mothod suitable far deep sub-half micron BC PMOSFETs, using the device simulator MEDICI. So we found out that the method of Halo Implantation could be applied to deep sub-half micron BC PMOSFETs for 255 Mbit DRAM.

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