• Journal of the Korean Crystal Growth and Crystal Technology
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• v.17 no.5
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• pp.187-191
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• 2007

The device performance of ZnO-thin film transistors(ZnO-TFTs) with gate dielectrics of $SiO_2,\;SiN_x$ and Polyvinylphenol(PVP) having a bottom gate configuration were investigated. ZnO-TFTs can induce high device performance with low intrinsic carrier concentration of ZnO only by controlling gas flow rates without additional doping or annealing processes. The field effect mobility and on/off ratio of ZnO-TFTs with $SiN_x$ were $20.2cm^2V^{-1}s^{-1}\;and\;5{\times}10^6$ respectively which is higher than those previously reported. The device adoptable values of the mobility of $1.37cm^2V^{-1}s^{-1}$ and the on/off ratio of $6{\times}10^3$ were evaluated from the device with organic PVP dielectric.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.6
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• pp.433-439
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• 2011

Poly Si TFTs (poly silicon thin film transistors) with p channel those are annealed HT (high temperature) with gate poly crystalline silicon and LT (low temperature) with metal gate electrode were fabricated on quartz substrate using the analyzed data and compared according to the activated grade silicon thin films and the size of device channel. The electrical characteristics of HT poly-Si TFTs increased those are the on current, electron mobility and decrease threshold voltage by the quality of particles of active thin films annealed at high temperature. But the on/off current ratio reduced by increase of the off current depend on the hot carrier applied to high gate voltage. Even though the size of the particles annealed at low temperature are bigger than HT poly-Si TFTs due to defect in the activated grade poly crystal silicon and the grain boundary, the characteristics of LT poly-Si TFTs were investigated deterioration phenomena those are decrease the electric off current, electron mobility and increase threshold voltage. The results of transconductance show that slope depend on the quality of particles and the amplitude depend on the size of the active silicon particles.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.248-249
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• 2008

ZnO (Zinc Oxide) thin film can be applied to various devices. Recently, ZnO film has been promoted in transparent TFTs (thin film transistors) because of high transparency and low temperature process. In this paper, ZnO thin films were grown on glass with the three conditions of RF sputtering power, which are 50W, 75W, 100W. Their structural, electrical and optical properties were investigated by using XRD, UV-Visible spectrometer and 4-point probes. In the ZnO film with 50W process, good crystallinity, high transmittance, and high sheet resistance were shown. In conclusion, the ZnO film with 50W can be an optimal channel layer of TFTs.

• Korean Journal of Materials Research
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• v.14 no.7
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• pp.516-521
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• 2004

We applied a deuterium plasma treatment to the surface of polycrystalline silicon films using PECVD and observed the change with AFM, XRD, ET-IR, and SIMS measurement. A bias temperature stressing (BTS) test was carried out to evaluate the reliability of the thin-film transistors (TFT). TFTs with channel lengths as small as 2 ${\mu}m$ were electrically stressed fer up to 1000 sec at room temperature. From the parameter variation such as s-factor, leakage current and on/off ratio, we suggest that the deuterium plasma treatment suppress the hot carrier effect and improve the stability of TFTs.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1412-1413
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• 2011

Effects of thermal annealing on electrical characteristics of thin film transistors (TFTs) using hydrogenated zinc oxide (ZnO:H) films as active channel were extensively investigated. The ZnO:H films were deposited at room temperature by RF sputtering. The device parameters of the ZnO:H-based TFTs, such as threshold voltage ($V_{th}$), subthreshold swing (S.S.), and on-off current ratio ($I_{on}/I_{off}$), were characterized in terms of the annealing temperature as well as the gas flow ratio of $H_2$/Ar.

• Journal of Information Display
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• v.12 no.4
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• pp.205-208
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• 2011

Herein, the integration of solution-processed polymer thin-film transistors (TFTs) that were fabricated using selective wettability through ultraviolet (UV) exposure into a reflective liquid crystal display is demonstrated. From the experimental results of energy-dispersive spectroscopy, the composition of carbon and fluorine enhancing the hydrophobicity in the polymer chains was found to play a critical role in the wetting selectivity upon UV exposure. The polymer TFTs fabricated through the wettability-patterning process exhibited long-term stability and reliability. This wetting-selectivity-based patterning technique will be useful for constructing different types of solution-processed electronic and optoelectronic devices.

• Transactions on Electrical and Electronic Materials
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• v.18 no.1
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• pp.51-54
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• 2017

TFTs (thin film transistors) were fabricated using a-SIZO (amorphous silicon-indium-zinc-oxide) channel by RF (radio frequency) magnetron sputtering at room temperature. We report the influence of various channel thickness on the electrical performances of a-SIZO TFTs and their stability, using TS (temperature stress) and NBTS (negative bias temperature stress). Channel thickness was controlled by changing the deposition time. As the channel thickness increased, the threshold voltage ($V_{TH}$) of a-SIZO changed to the negative direction, from 1.3 to -2.4 V. This is mainly due to the increase of carrier concentration. During TS and NBTS, the threshold voltage shift (${\Delta}V_{TH}$) increased steadily, with increasing channel thickness. These results can be explained by the total trap density ($N_T$) increase due to the increase of bulk trap density ($N_{Bulk}$) in a-SIZO channel layer.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.396-399
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• 2009

Thin-film transistors (TFTs) with an aluminum indium oxide (AIO) channel layer were fabricated via a simple and low-cost sol-gel process. Effects of annealing temperature and time were investigated for better TFT performance. The sol-gel AIO TFTs were annealed as low as $350^{\circ}C$. They exhibit n-type semiconductor behavior, a mobility higher than 19 $cm^2/V{\cdot}s$ and an onto-off current ratio greater than $10^8$.

• Journal of Information Display
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• v.12 no.1
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• pp.61-67
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• 2011

A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31" WVGA ($800{\times}480$) LCD panel, and the fabricated circuits were verified via simulations and measurements.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.7
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• pp.415-418
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• 2015

In this paper, $TiO_2$ based thin-film transistors (TFTs) were fabricated using by an atomic layer deposition with high aspect ratio and excellent step coverage. $TiO_2$ semiconducting layer was deposited showing a rutile phase through the rapid thermal annealing process, and exhibited TFT characteristics with a $200{\mu}m$ channel length of low-leakage currents (none of current flow during off-state), stable threshold voltages (-10 V ~ 0 V), and a much higher on/off current ratio (<$10^5$), respectively.