• Proceedings of the KSME Conference
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• 2007.05b
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• pp.2453-2458
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• 2007

The performance of polysilicon thin film transistor (p-Si TFT) has an important role in the operation of active matrix liquid crystal displays. To fabricate the p-Si TFTs that have uniform characteristics, understanding of the recrystallization mechanism of silicon is crucial. Especially, the analysis of the transient temperature variation and the liquid-solid interface motion is required to find the mechanism. The thermal conductivity is one of the most important parameters to understand the mechanism. In this work, a KrF eximer laser beam was irradiated to amorphous silicon thin films. We measured the transient reflectivity at the wavelength of 633 nm. We carried out the numerical simulation of one dimension conduction equation so that we determined the most well-fitted thermal conductivity by comparing the numerically obtained transient reflectivity with the experimentally measured one. The experimentally determined thermal conductivity of amorphous silicon thin films is 1.5 W/mK.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1459-1462
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• 2008

In this paper we describe solutions to address critical challenges in direct fabrication of amorphous silicon thin film transistor (TFTs) arrays for active matrix flexible displays. For all flexible substrates a manufacturable handling protocol in automated display-scale equipment is required. For metal foil substrates the principal challenges are planarization and electrical isolation, and management of stress (CTE mismatch) during TFT fabrication. For plastic substrates the principal challenge is dimensional instability management.

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.19-20
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• 2000

We have developed the 12.1" SVGA reflective type color TFT-LCD(Thin Film Transistor - Liquid Crystal Display) with the high aperture ratio and well designed reflector for the applications such as mini note PC, Note PC and electronic book. The panel shows the high reflectance(30%) and contrast ratio(20:1) resulted from optimizing the optical films and designing the embossing shaped reflector. By improving the chromacity, the color reproducibility was increased up to 20%. As removing the backlight unit, we reduced the power consumption, thickness and weight of the panel to 0.8W, 2.2mm, and 250gram, respectively. According to the above performances, we have obtained fabrication process for mass production, and furthermore, could have access to fast market launching.

• Proceedings of the KIEE Conference
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• 2005.07c
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• pp.1884-1886
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• 2005

KrF 펄스 레이저 증착법(pulsed laser deposition: PLD)으로 ZnO 박막을 증착하여 평판 디스플레이 소자 구동용 박막 트랜지스터(thin film transistor) 소자를 제작하였다. 전도성이 높은 실리콘웨이퍼(c-Si, 하부전극) 기판 위에 LPCVD 법으로 silicon nitride 박막을 절연막으로 형성하고, 다양한 공정 조건에서 펄스 레이저 증착법으로 제작한 ZnO 박막을 증착하여 채널층으로 하였으며, Al 박막을 증착하고 패터닝하여 소스 및 드레인 전극으로 하였다. ZnO 박막의 증착 시에 기판 온도를 다양하게 조절하고 산소 분압을 변화시켜 ZnO 박막의 특성을 조절하였다. 제작된 박막의 표면특성은 AFM(atomic force microscopy)로 분석하고, 결정특성은 XRD(X-ray diffraction)로 조사하였다. ZnO 박막의 전기적 특성은 Hall-van der Pauw 법으로 측정하였고, 광학 투과도(optical transparency)를 UV-visible photometer로 조사하였다. ZnO-TFT 소자는 $10^6$ 수준의 on-off ratio와 $2.4{\sim}6.1cm^2/V{\cdot}s$의 전계효과이동도(field effect mobility)를 보였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.120-121
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• 2007

Nano-floating gate memory (NFGM) devices were fabricated by using the low temperature poly-Si thin films crystallized by ELA and the $In_2O_3$ nano-particles embedded in polyimide layers as charge storage. Memory effect due to the charging effects of $In_2O_3$ nano-particles in polyimide layer was observed from the TFT NFGM. The post-annealing in 3% diluted hydrogen $(H_2/N_2)$ ambient improved the retention characteristics of $In_2O_3$ nano-particles embedded poly-Si TFT NFGM by reducing the interfacial states as well as grain boundary trapping states.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1473-1474
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• 2011

박막트랜지스터(Thin Film Transistor: TFT)의 게이트 절연층 에서는 박막의 전계강도, 고유전율 및 우수한 표면 특성이 요구된다. HD-PECVD(High Density - Plasma Enhanced Chemical Vapor Deposition)를 이용하여 $NH_3$ 유량 및 기판 온도를 변화시키면서 SiN 박막을 제작하고, 표면특성을 AFM 으로, CONTACT ANGLE로 접촉각을 측정하여 Young's Equation 으로 Surface Energy를 계산하였고 전기적 특성은 MIM 구조를 제작하고 C-V 측정을 하여 조사하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.11a
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• pp.3-6
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• 1992

A new analytical expression for the saturated I-V characteristics of hydrogenerated amorphous silicon thin film transistors(a-si:H TFT) is presented and experimentally verified. The results show that the experimental transfer and output characteristics at several temperatures are easily modeled. The model is based on three functions obtained from the experimental data of $I_D$ versus $V_G$. Theoretical results confirm the simple form of the model in terms of the device geometry. It was determined that the saturated drain current increased at a fixed gate voltage and the device saturated at increasingly larger drain voltages while the threshold voltages decreased.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.201-204
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• 2001

In this paper, for modeling of electrical characteristics in Poly Silicon Thin Film Transistors with process parameters set up optimum values, So, the I-V characteristics of poly silicon TFT parameters are examined and simulated in terms of the variations in process parameter. And these results compared and analyzed simulation values with examination value. The simulation program for characteristic analysis used SUPREM IV for processing, Matlab for modeling by mathematics, and SPICE for electric characteristic of devices. Input parameter for simulation characteristics is like condition of device process sequence, these electric characteristic of $I_D-V_D$ $I_D-V_G$, variations of grain size. The Gate oxide thickness of poly silicon are showed similar results between real device characteristics and simulation characteristics.

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.15-16
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• 2000

The gate bias stress effect of the hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) with a $SiN_x/BCB$ gate insulator have been studied. The gate planarization was carried out by spin-coating of BCB (benzocyclobutene) on Cr gates. The BCB exhibits charge trappings during a high gate bias, but the stability of the TFT is the same as conventional one when it is between -25 V and +25 V. The charge trap density in the BCB increases with its thickness.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.64-66
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• 2009

We obtained high performance of n-type organic thin film transistors (OTFTs) using a solution process. N, N' bis-(octyl-)-dicyanoperylene-3,4:9,10-bis(dicarboximide) (PDI-$8CN_2$) in ambient air. Low work function interlayer on source/drain is needed to enhance the electron injection to low LUMO level of n-type organic semiconductor. By using self-assembled monolayer (SAM) the field-effect mobility of 0.33 $cm^2$/Vs was achieved.