• 산업공학
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• 제16권4호
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• pp.463-472
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• 2003

In this study we consider the problem of MPS(master production planning) of TFT-LCD(Thin Film Transistor - Liquid Crystal Display) production factory. Due to the complexities of the TFT-LCD production processes, it is difficult to build effective MPS. This study presents an algorithm having a concept of IDPQ(Ideal Daily Production Quantity) that considers line balancing of TFT-LCD production process. In general, the MPS building procedure does not consider line balancing in non-bottleneck processes. MPS without considering line balancing may make ineffective schedule. We present algorithms for building MPS considering factory capacity and line balancing according to the sales order.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1281_1282
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• 2009

ICP-CVD를 이용하여 inverted staggered 구조를 갖는 미세결정 실리콘 (Nanocrystalline Silicon, nc-Si) 박막 트랜지스터(Thin Film Transistor, TFT)를 제작하였다. 또한, 소자의 특성과 전기적 안정성을 평가하였다. 실험 결과는 짧은 채널 길이를 갖는 nc-Si TFT가 긴 채널 길이의 소자보다 같은 드레인 전압 바이어스 하에서 덜 열화 됨을 알 수 있었다. 이는 드레인 전압 바이어스 하에서의 낮은 채널 캐리어 농도는 적은 defect state를 만들기 때문으로 짧은 채널 길이의 TFT가 긴 채널 길이의 TFT보다 $V_{TH}$ 열화가 적었다. 이러한 결과는 짧은 채널 길이의 nc-Si TFT가 디스플레이 분야에 있어 다양하게 응용될 것으로 기대된다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.747-751
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• 2006

The hydrogenated amorphous silicon thin film transistor (a-Si:H TFT) with copper as source and drain electrode has been fabricated to obtain its transfer characteristics and stressed with positive and negative bias to investigate the instability variation comparing to conventional MoW-Al based TFT device. The results show that there is no copper diffusion into active layer of a-Si:H TFT, even during the thermal process. In addition, a 15-inch XGA a Si:H TFT LCD display utilizing Cu as gate electrodes has been developed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 추계학술대회 논문집 학회본부 C
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• pp.452-454
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• 2000

In recent years, the Thin Film Transistor Liquid Crystal Display (TFT-LCD) is used in a variety of products as an interfacing device between human and them. Since TFT-LCDs have trend toward larger Panel sizes and higher spatial and/or gray-scale resolution, pixel charging characteristic is very important for the large panel size and high resolution TFT-LCD pixel characteristics. In this paper, both data line precharging method and line time extension (LiTEX) method is applied to Pixel Design Array Simulation Tool (PDAST) and the pixel charging characteristics of TFT-LCD array were simulated, which were compared with the results calculated by both PDAST In which the conventional device model of a-Si TFTs and gate step method is implemented.

• 전자공학회논문지
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• 제52권7호
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• pp.33-39
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• 2015

본 연구에서는 SU-8을 절연층으로 사용해 솔루션 공정을 바탕으로 하여 Indium Zinc Oxide(IZO) thin film transistor(TFT)의 안정성을 향상에 대해 연구하였다. 매우 점성이 강하며 negative lithography 용으로 사용되는 SU-8은 기계적, 화학적으로 높은 안정도를 가진다. 그리고 이 SU-8을 사용해 TFT층의 위에 스핀코팅을 사용해 절연막 층을 쌓고 photo lithography를 이용해 patterning을 하였다. SU-8층에 의한 positive bias stress(PBS)에 대한 전기적 특성 향상의 이유를 연구하기 위해 TFT에 X-ray photoelectron spectroscopy(XPS), Fourier transform infrared spectroscopy(FTIR) 분석을 시행하였다. SU-8을 절연층으로 한 TFT는 좋은 전기적 특성을 보였으며, 전류점멸비, 전자이동도, 문턱전압, subthreshold swing이 각각 $10^6$, $6.43cm^2/V{\cdot}s$, 7.1V, 0.88V/dec로 측정되었다. 그리고 3600초 동안 PBS를 가할 시 ${\Delta}V_{th}$는 3.6V로 측정되었다. 그러나 SU-8 층이 없는 경우 ${\Delta}V_{th}$는 7.7V 였다. XPS와 FTIR을 분석한 결과, SU-8 절연층이 TFT의 산소의 흡/탈착을 차단하는 특성에 의해 PBS에 강한 특성을 나타나게 함을 확인하였다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권1호
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• pp.24-29
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• 2000

We propose a simple method to control the crystallization depth of amorphous silicon (a-Si) deposited by PECVD or LPCVD during the excimer laser annealing (ELA). Employing the new method, we have formed poly-Si/a-Si double film and fabricated a new poly-Si TFT with vertical a-Si offsets between the poly-Si channel and the source/drain of TFT without any additional photo-lithography process. The maximum leakage current of the new poly-Si TFT decreased about 80% due to the highly resistive vertical a-Si offsets which reduce the peak electric field in drain depletion region and suppress electron-hole pair generation. In ON state, current flows spreading down through broad a-Si cross-section in the vertical a-Si offsets and the current density in the drain depletion region where large electric field is applied is reduced. The stability of poly-Si TFT has been improved noticeably by suppressing trap state generation in drain region which is caused by high current density and large electric field. For example, ON current of the new TFT decreased only 7% at a stress condition where ON current of conventional TFT decreased 89%.

• 한국컴퓨터정보학회논문지
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• 제12권4호
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• pp.249-256
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• 2007

본 논문에서는 휴대 가능한 중소형($4{\sim}9$인치 크기)의 정보단말기에 사용되는 TFT-LCD(Thin Film Transistor addressed -Liquid Crystal Display)의 LDI(LCD Driver Interface) 제어기(controller)를 제조사와 크기에 관계없이 사용할 수 있는 표준화된 범용 TFT-LCD의 LDI를 설계하고 FPGA(Field Programmable Gate Array)로 구현하였다. 설계한 LDI 제어기는 FPGA 테스트 보드(test board)에서 검증하였으며, 상업용 TFT-LCD 패널에서 시험결과 안정적으로 상호 동작하였다. 설계한 범용 LDI 제어기의 장점은 LCD의 제조사와 크기에 관계없이 그 동작을 표준화시켜 설계하였으므로 향후 모든 패널내의 SoG(System on a Glass) 모듈 설계에 적용할 수 있는 것이다. 그리고 기존의 방식에서는 LCD 제조사별, 패널 크기별로 별개의 LDI 제어기 칩을 개발하여 사용하지만, 설계한 LDI 제어기는 모든 휴대 가능한 중소형 패널을 구동시킬 수 있어서 IC의 공급가, AV 보드와 패널의 제조 원가 하락을 가져올 수 있으며 가까운 장래에는 보다 우수한 기능의 패널을 제작하기 위한 TFT-LCD 패널 모듈의 SoG 개발이 필연적으로 요구되고 있다. 연구결과는 TFT-LCD 패널을 더욱 소형화, 경량화 그리고 저가격화가 가능하여 기술 및 시장 경쟁력을 선점할 수 있다. 또한 향후 많은 수요가 예상되는 이동형 정보단말기에 사용되는 TFT-LCD 패널 모듈의 SoG IC(Integrated Circuit) 개발과 제작을 위한 기초 자료로서 활용될 수 있다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 D
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• pp.1809-1811
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• 1999

In recent years, attempts have been made to greatly improve the display quality of active-matrix liquid crystal display devices, and many techniques have been proposed to solve such problems as gate delay, feed-through voltage and image sticking. Gate delay is one of the biggest limiting factors for large-screen-size, high-resolution thin-film transistor liquid crystal display (TFT/LCD) design. Many driving method proposed for TFT/LCD progress. Thus we developed gate driving signal generator. Since Pixel-Design Array Simulation Tool (PDAST) can simulate the gate, data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the driving signals of gate lines on the pixel operations can be effectively analyzed.

• Industrial Engineering and Management Systems
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• 제8권3호
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• pp.148-154
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• 2009

In recent days, large-sized flat-panel display (FPD) has been increasingly applied to computer monitors and TVs. Mura defects, appearing as low contrast or non-uniform brightness region, sometimes occur in manufacturing of the Thin-Film Transistor Liquid-Crystal Displays (TFT-LCD). Implementation of automatic Mura inspection methods is necessary for TFT-LCD production. Various existing Mura detection methods based on regression diagnostics, surface fitting and data transformation have been presented with good performance. This paper proposes an efficient Mura detection method that is based on a regression diagnostics using studentized residuals for automatic Mura inspection of FPD. The input image is estimated by a linear model and then the studentized residuals are calculated for filtering Mura regions. After image dilation, the proposed threshold is determined for detecting the non-uniform brightness region in TFT-LCD by means of monitoring the every pixel in the image. The experimental results obtained from several test images are used to illustrate the effectiveness and efficiency of the proposed method for Mura detection.

• E2M - 전기 전자와 첨단 소재
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• 제9권3호
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• pp.277-283
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• 1996

The temperature dependent characteristics of hydrogenerated amorphous silcon thin film transistor (a-Si:H TFT) with a bottom gate of N-Type <100> Si wafer were investigated. Drain current on the hysteresis characteristic curve showed an exponential variation. Hysteresis area of TFT increased with the gate voltage increased and decreased with the small gate voltage. According to the variation of gate voltages, drain current of TFT increased by temperature increase, and hysteresis characteristics mainly depended on the temperature increase. The hysteresis current showed negative characteristics curve over 383K. The hysteresis occurance area and the differences of forward and reverse sweep were increased at the higher temperature. Hysteresis current of I$_{d}$(on/off) ratio decreased at the lower temperature and increased at the higher temperature.e.