• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.11a
• /
• pp.80-81
• /
• 2008

Schottky barrier thin film transistors (SB-TFT) on polycrystalline silicon(poly-Si) are fabricated by platinum silicided source/drain for p-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method. The fabricated poly-Si SB-TFTs showed low leakage current level and a large on/off current ratio larger than $10^5$. Significant improvement of electrical characteristics were obtained by the additional forming gas annealing in 2% $H_2/N_2$ ambient, which is attributed to the termination of dangling bond at the poly-Si grain boundaries as well as the reduction of interface trap states at gate oxide/poly-Si channel.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1999.05a
• /
• pp.589-592
• /
• 1999

This paper describes direct $\mu$C-Si/CaF$_2$/glass thin film growth by RPCVD system in a low temperature for thin film transistor (TFT), photovoltaic devices. and sensor applications. Experimental factors in a low temperature direct $\mu$ c-Si film growth are presented in terms of deposition parameters: SiH$_4$/H$_2$ ratio, chamber total pressure, substrate temperature, rf power, and CaF$_2$ buffer layer. The structural and electrical properties of the deposited films were studied by means of Raman spectroscopy, I-V, L-I-V, X-ray diffraction analysis and SEM. we obtain a crystalline volume fraction of 61%, preferential growth of (111) and (220) direction, and photosensitivity of 124. We achieved the improvement of crystallinity and electrical property by using the buffer layers of CaF$_2$ film.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2008.10a
• /
• pp.258-260
• /
• 2008

Developed halftone exposure technique was successfully applied to the fabrication of narrow transistor channels below $4\;{\mu}m$ with conventional photolithography method. Asymmetric slits concept of photo mask was applied to make channel lengths (L) shorter for thin film transistor's (TFT) high performance. These short channel TFTs verified better quality transistor characteristics.

• Electrical & Electronic Materials
• /
• v.17 no.8
• /
• pp.3-12
• /
• 2004

유기 박막 트랜지스터 (Organic Thin film Transistors ； 이하 OTFT)는 1986년부터(1) 반도체 장치의 새로운 부류로 급속하게 발전해 오고 있다. 반도체 산업에 있어 이러한 유기물질의 큰 발전은 1947년에 있었던 최초의 inorganic FET (Field Effect Transistor) 탄생에 버금갈 만한 성과라고 여겨진다.(중략)

• Proceedings of the IEEK Conference
• /
• 2000.06b
• /
• pp.314-317
• /
• 2000

In order to analyze the characteristics of complicated TFT-LCD (Thin Film Transistor-Liquid Crystal Display) circuits, it is indispensible to use simulation programs. In this study, we present a systematic method of extracting the input parameters of poly-Si TFT for Spice simulation. This method is applied to two different types of poly-Si TFTs fabricated in our group with good results. Among the Spice simulators, Pspice has the graphic user interface feature making the composition of complicated circuits easier. We added successfully a poly-Si TFT model on the Pspice simulator, which would contribute to efficient simulations of poly-Si TFT-LCD pixels and arrays.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2007.06a
• /
• pp.93-94
• /
• 2007

다양한 LDD(lightly doped drain)에 따른 n-channel poly-Si TFT (thin film transistor)에 대하여 보고한다. 유리 기판 위에 ELA를 이용하여 만들어진 Polycrystalline silicon (poly-Si)은 TFT-LCD의 응용을 위한 재료로써 우수한 특성을 갖는다. 제작된 n-channel TFT는 절연층으로 $SiN_x$, $SiO_2$의 이중 구조를 갖는다. 다양한 LDD에 따른 n-channel poly-Si TFT의 문턱전압($V_{TH}$), ON/OFF 전류비 ($I_{ON}/I_{OFF}$), 포화전류($I_{DSAT}$)는 TFT의 보다 좋은 성능을 위해 연구된다. 짧은 LLD 길이를 가진 n-channel poly-Si TFT의 문턱전압은 작고, 포화전류의 값은 크다. 또한 긴 LLD 길이를 가진 n-channel poly-Si TFT는 작은 kink effect를 가진다.

• Journal of Information Display
• /
• v.10 no.1
• /
• pp.33-36
• /
• 2009

A new hybrid silicon thin-film transistor (TFT) fabrication process using the DPSS laser crystallization technique was developed in this study to realize low-temperature poly-Si (LTPS) and a-Si:H TFTs on the same substrate as a backplane of the active-matrix liquid crystal flat-panel display (AMLCD). LTPS TFTs were integrated into the peripheral area of the activematrix LCD panel for the gate driver circuit, and a-Si:H TFTs were used as a switching device of the pixel electrode in the active area. The technology was developed based on the current a-Si:H TFT fabrication process in the bottom-gate, back-channel etch-type configuration. The ion-doping and activation processes, which are required in the conventional LTPS technology, were thus not introduced, and the field effect mobility values of $4\sim5cm^2/V{\cdot}s$ and $0.5cm^2/V{\cdot}s$ for the LTPS and a-Si:H TFTs, respectively, were obtained. The application of this technology was demonstrated on the 14.1" WXGA+(1440$\times$900) AMLCD panel, and a smaller area, lower power consumption, higher reliability, and lower photosensitivity were realized in the gate driver circuit that was fabricated in this process compared with the a-Si:H TFT gate driver integration circuit

• Journal of the Microelectronics and Packaging Society
• /
• v.14 no.3
• /
• pp.15-20
• /
• 2007

Low temperature processed ZnO-TFTs on glass below $270^{\circ}C$ for plastic substrate applications were fabricated and their electrical properties were investigated. Films in ZnO-TFTs with bottom gate configuration were made by RF magnetron sputtering system except for $SiO_2$ gate oxide deposited by ICP-CVD. ZnO channel films were grown on glass with various Ar and $O_2$ flow ratios. All of the fabricated ZnO-TFTs showed perfectly the enhancement mode operation, a high optical transmittance of above 80% in visible ranges of the spectrum. In the ZnO-TFTs with pure Ar process, the field effect mobility, threshold voltage, and on/off ratio were measured to be $1.2\;cm^2/Vs$, 8.5 V, and $5{\times}10^5$, respectively. These characteristic values are much higher than those of the ZnO-TFTs of which ZnO channel layers were processed with additional $O_2$ gas. In addition, ZnO-TFT with pure Af process showed smaller swing voltage of 1.86v/decade compared to those with $Ar+O_2$ process.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.3
• /
• pp.39-46
• /
• 1994

CMOS LCD driving circuits using poly-Si TFT have been designed and basic blocks including test patterns have been fabricated. Column driver drives the pixels by block because polu-Si TFT can not operate at the speed of video signal. Row driver has mode selection circuit which can select a mode between interlacing mode and non-interlacing mode. Experimental results show shift register can operate at 1MHz colck frequency with 4pF load.

• Proceedings of the IEEK Conference
• /
• 2000.06b
• /
• pp.322-325
• /
• 2000

N-channel poly-Si TFT, Processed by Solid Phase Crystalline(SPC) on a glass substrate, has been investigated by measuring its electrical properties before and after electrical stressing. It is observed that the threshold voltage shift due to electrical stress varies with various stress conditions. Threshold voltages measured in 1.5$\mu\textrm{m}$ and 3$\mu\textrm{m}$ poly-Si TFTs are 3.3V, 3.V respectively. With the threshold voltage shia the degradation of transconductance(G$\_$m/) and subthreshold swing(S) is also observed.