• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.40 no.7
• /
• pp.273-281
• /
• 2003

This paper proposes a new time synchronization scheme for the Automatic Identification System(AIS). The proposed scheme utilizes a Temperature Compensated Crystal Oscillator(TCXO) as a local reference clock, and consists of a Digitally Controlled Oscillator(DCO), a divider, a phase comparator, and register blocks. Primary time reference is IPPS from GPS receiver that is synchronized to Universal Time Coordinated(UTC). And if GPS is unavailable, other station's signal is utilized as secondary time reference. The phase comparator measures time difference between the 1PPS and the generated transmit clock. The measured time difference is compensated by controlling the DCO and the transmit clock is synchronized to the Universal Time Coordinated(UTC). The synchronized transmit clock(9600Hz) is divided into the transmitting time slot(37.5Hz). The proposed scheme is tested in an experimental AIS transponder set. The experimental result shows that the proposed module satisfies the timing specification of the AIS technical standard, ITU-R M.1371-1.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.23 no.8
• /
• pp.2064-2071
• /
• 1998

A new digital clock level translator has been designed in order to produce a clock source of the internal logic circuits. The translator output has 50% duty ratio from small sinusoidal input such as TCXO which oscillates itself in poratable components. The circuit consists of positive and negative comparators, RS latch, charge pump, and reference vol- tage generator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator reference, producing output waveform with valid 50% duty ratio of the digital signal level. The designed level translator can be used as a sampling clock source of ADC, PLL and the colck source of the clock synthesizer. The circuit wasdesigned in a 0.8.mu.m analog CMOS technology with double metal, double poly, and BSIM3 circuit simulation model. From our experimental results, a stable operating characteristics of 50 +3% duty ratio was obtained from the sinusoidal input wave of 370 mV.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2003.11a
• /
• pp.74-74
• /
• 2003

적외선 감지기는 냉장고, 에어컨, 자동차용 전자부품 등의 온도측정 및 제어, 과잉 전류의 억제를 위한 소자로 널리 사용되며, 또한 최근에는 온도보상형 수정발진기(TCXO) 또는 RF모듈, 액정 판넬의 온도보상회로 등 정보통신기기의 신뢰성 향상을 위해 그 수요가 날로 증가하고 있다. 현재 상용되는 적외선 감지기의 대부분은 벌크형 또는 후막형으로 제조되고 있으나, 최근 반도체공정 기술의 발달로 인하여 보다 향상된 특성이 요구됨에 따라 박막형 등 새로운 형태의 적외선 감지기 대해 활발한 연구가 이루어지고 있다. 본 연구에서는 열 질량과 전도에 의한 열손실을 최소화하여 소자의 감도 및 응답 특성을 향상시키기 위하여 SiO$_2$Si$_3$N$_4$/SiO$_2$ (ONO)다중층 위에 소자 감지부를 형성하고 bulk-micromachining기술을 이용하여 멤브레인 구조를 갖는 박막형 적외선 감지기를 제작하였다.

• Proceedings of the KIEE Conference
• /
• 2005.07d
• /
• pp.2573-2575
• /
• 2005

본 논문에서는 원자 시계를 이용한 위성 시계 고장 판단 기법을 제안한다. GPS 측정치 중 위성 시계 오차 성분을 제외한 위성 궤도 오차, 이온층 지연 오차, 대류층 지연 오차, 수신기 시계 오차를 제거하여 위성 시계 오차에 의한 영향만을 검사하도록 한다. 특히 TCXO와 같은 일반적인 수신기 시계를 사용할 경우 정확한 수신기 시계 오차 크기를 추정하기 어렵기 때문에 원자 시계와 같은 정밀 신호 발생기를 이용하여 수신기 시계 오차에 의한 영향을 제거하는 방법을 제시한다. 제시한 방법은 실제 위성 시계에 이상이 발생 했을 때 수집한 데이터를 이용한 실험을 통하여 검증하도록 한다.

• Journal of Korea Society of Industrial Information Systems
• /
• v.18 no.5
• /
• pp.9-14
• /
• 2013

This paper is designed frequency multiplier with low phase noise using DLL technique. The VCDL is designed using a differential structure to reduce common-mode noise. The proposed frequency multiplier is fabricated in a 65nm, 1.2V TSMC CMOS process, and the operating frequency range from 10MHz to 24MHz was measured. The SSB phase noise is measured to be -125dBc/Hz at 1MHz from 38.4MHz carrier. A total area of $0.032mm^2$were consumed in the chip, including the output buffer. Total current is 1.8mA at 1.2V supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.11 no.5
• /
• pp.715-722
• /
• 2000

In this paper, the PLDRO is designed and implemented for X-band. It is comprised of tunable high Q resonator with a varactor diode for frequency tuning, loop filter and a 1/8 prescaler which up to 10GHz. Also, it is implemented a TCXO and a VCO signal into the phase detector and achieved a highly stable signal source. From the measurement, the designed PLDRO has the output power of 2.5dBm at 8GHz and phase noise of -64.33dBc at 10KHz offset from carrier. Its characteristic is 26 dBc. This PLDRO has much better temperature stability.

• Journal of Institute of Control, Robotics and Systems
• /
• v.20 no.6
• /
• pp.669-675
• /
• 2014

In this paper, we described the investigated theoretical time synchronization performances and experiment results obtained by commercially provided PTP (Precise Time Protocol) modules when the time of a slave clock is synchronized to the master clock. In the case of the theoretical performance analysis, we investigated 3 types of clock levels such as Crystal Oscillator (XO), TCXO (Temperature Compensated XO) and OCXO (Oven Controlled XO). From the analysis, it was observed that the synchronization performance is greatly influenced by the synchronization period and the required performance under 1 us can be achieved by using XO level clocks when the synchronization period is less than 2 seconds and the uncertainty of the propagation delay is under 100 ns. For the experiments using commercial PTP modules, the synchronization performance was investigated for direct, through 1 hub and through 2 hubs connections between the master clock and the slave clock. From the experiment results, we observed that time synchronization under 90 ns with 1,000 seconds observation interval can be achieved in the case of direct connection.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.3A
• /
• pp.237-246
• /
• 2007

Clock Synchronization is one of the most basic factors to be considered when we implement an indoor synchronization network for indoor positioning. In this paper, we present a new synchronization algorithm which does not employ time stamps in order to reduce the hardware complexity and data overhead. In addition to that, we describe an algorithm that is designed to compensate the frequency drift giving an serious impact on the synchronization performance. The performance evaluation of the proposed algorithm is achieved by investigating MTIE (Maximum Time Interval Error) values through simulations. In the simulations, the frequency drift values of the practical oscillators are used. From the simulation results, it is investigated that we can achieve the synchronization performance under 10 ns when we use 1 second synchronization interval with 1 ns resolution and TCXOs (Tmperature Compensated Cristal Oscillators) both in the master clock and the slave clock.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.5 no.4
• /
• pp.653-660
• /
• 2001

In this paper, we designed 2303.15MHz frequency synthesizer for the purpose of the phase noise prediction. For the modeling of phase noise generated in the designed system through introducing the noise-modeling method suggested by Lascari we analyzed a variation of phase noise as according as that of offset frequency. Especially, for the third-order system of the PLL among some kinds of phase noise generated from VCO we analyzed the aspect of 1/f-noise appearing troubles in the low frequency band. Since it is difficult to analyze mathematically 1/f-noise in the third-order system of the PLL, introducing the concept of pseudo-damping factor has made an ease of the access of the 1/f-noise variance. we showed a numerical formula of 1/f-noise variance in the third-order system of the PLL which is compared with that of 1/f-noise variance in the second-order system of the PLL. As a result, In case of txco we found the reduce rapidly along the offset frequency after passed through that phase-noise was -160dBc/Hz before passed through a loop at 10kHz offset frequency and -162.6705dBc/kHz after passed through the loop, -180dBc/Hz at 100kHz offset frequency and -560dBc/kHz after passed through the loop. We can notice that the variance of third-order system more occurs (or the variance of second-order system in connection with noise bandwidth and variance factor of second-order and third-order system.