• Proceedings of the Korea Multimedia Society Conference
• /
• 2001.11a
• /
• pp.30-34
• /
• 2001

본 논문에서는 근거리에 놓여있는 노트북, 휴대폰, PDA, 혜드셋 등 각종 이동 가능한 장치들을 하나의 무선네트워크로 연결할 수 있는 블루투스의 베이스밴드 시스템 프로토콜 기능을 분석하고 설계하였다. 즉, 전체적인 논리 기능구조를 설계한 후 하드웨어로 구현될 패킷생성 블록, HEC와 CRC 기능블륵, Whitening/Dewhitening 기능블록, FEC 기능블록, 입출력 블록(TX, RX 루틴), 클럭 생성 기능블록, 주파수 선별 기능블록, 오디오 기능블록 그리고, 패킷 제어 블록들의 처리절차를 Verilog HDL 코드로 설계 및 검증하였다.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.93-96
• /
• 2002

It is said that the verification effort occupies about 50-70 percent of the total effort of a System-On-A-Chip. This paper aims to develop a test bench automation tool based on the abstraction of the interface protocols. This tool will allow designers to describe their test benches in a high level language such as C rather than VHDL or Verilog. It helps designers to save their verification time and effort.

• Proceedings of the Korean Information Science Society Conference
• /
• 2001.10c
• /
• pp.22-24
• /
• 2001

내장형 시스템은 산업 전반에 다양한 방법으로 응용되고 있다. 하지만 항공 분야나 원자력 분야의 내장형 시스템은 안정성과 신뢰성이 절대적으로 보장되어야 하는 시스템으로 피 설계부터 구현에 이르기까지 다양한 방법으로 검사되고 검증되어야 한다. 본 논문에서는 내장형 시스템의 통합설계를 위한 기반으로 하드웨어 설계 언어인 Verilog를 입력 언어로 받아들여 이를 정형검증 도구인 VIS를 통하여 검증한 다음 이를 바로 구현하는 방법론 및 예를 보이고자 한다. 이러한 방법을 통해 내장형 시스템의 안정성과 신뢰성의 수준을 향상시키고자 한다.

• Proceedings of the Korea Society for Simulation Conference
• /
• 1999.04a
• /
• pp.232-236
• /
• 1999

Codesign 방법론은 하드웨어와 소프트웨어가 공존하는 시스템을 설계할 때 이드의 설계를 각각의 특성에 맞는 방법을 사용함으로써 효율적인 디자인방법을 제공한다. 전체 시스템의 동작 및 성능을 검증하기 위해서는 다른 방법으로 개발된 하드웨어와 소프트웨어를 같이 시뮬레이션해야 하는데 이를 통합시뮬레이션(Co-simulation)이라고 한다. 하드웨어와 소프트웨어를 개발하는 방법이 다르기 때문에 야기되는 통합의 문제점을 해결하기 위하여 DEVS(Discrete Event System Specification)에 기반한 중간단계형태를 통한 변환방법론을 제시하고 이를 사용하여 C++ 모델과 Verilog HDL 모델간의 통합시뮬레이션을 구현함으로써 효용을 보이고자 한다.

• Proceedings of the IEEK Conference
• /
• summer
• /
• pp.285-288
• /
• 2004

In this paper, we present a design and experiment of PCI Express core verification model. The model targeting Endpoint core based on Verilog HDL is designed by newly-emerging SystemC, which is a new C++ class library based system design approach. In the verification model, we designed and implemented a SystemC host system model which acted as Root Complex and device driver dedicated to the PCI Express Endpoint RTL core. The verification process is scheduled by scenarios which are implemented in host model. We show that the model is useful especially for verifying the RTL model which has dependencies on system software.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.12
• /
• pp.9-19
• /
• 1997

This paper describes the design and FPGA implementation of a system control unit within a multiprocessor chip which can be used as a node processor ina massively parallel processing (MPP) caches, memory management units, a bus unit and a system control unit. Major functions of the system control unit are locking/unlocking of the shared variables of protected access, synchronization of instruction execution among four integer untis, control of interrupts, generation control of processor's status, etc. The system control unit was modeled in very high level using verilog HDL. Then, it was simulated and verified in an environment where trap handler and external interrupt controller were added. Functional blocks of the system control unit were changed into RTL(register transfer level) model and synthesized using xilinx FPGA cell library in synopsys tool. The synthesized system control unit was implemented by Xilinx FPGA chip (XC4025EPG299) after timing verification.

• Journal of Korea Multimedia Society
• /
• v.5 no.2
• /
• pp.206-214
• /
• 2002

In this paper, it is designed and verified the baseband system that performs various protocol functions of specification of the Bluetooth system. In order to verify the developed circuits, various baseband functions are tested by using the ModelSim simulator. The developed circuits operate at 4MHz main clock. Test suite includes hap selection function, generation of the sync word, error correction(1/3 rate FEC, 2/3 rate FEC), HEC generation/checking, CRC generation/checking, data whitening/dewhitening and packet trans/reception procedure. etc. As a result of the simulation, it is verified that the developed baseband system conform to the specification of the Bluetooth system.

• Journal of the Semiconductor & Display Technology
• /
• v.19 no.3
• /
• pp.106-111
• /
• 2020

In this paper, we propose the non-contact gesture recognition system and algorithm using proximity-based sensors. The system uses four IR receiving photodiode embedded on a single chip and an IR LED for small area. The goal of this paper is to use the proposed algorithm to solve the problem associated with bringing the four IR receivers close to each other and to implement a gesture sensor capable of recognizing eight directional gestures from a distance of 10cm and above. The proposed system was implemented on a FPGA board using Verilog HDL with Android host board. As a result of the implementation, a 2-D swipe gesture of fingers and palms of 3cm and 15cm width was recognized, and a recognition rate of more than 97% was achieved under various conditions. The proposed system is a low-power and non-contact HMI system that recognizes a simple but accurate motion. It can be used as an auxiliary interface to use simple functions such as calls, music, and games for portable devices using batteries.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.29B no.10
• /
• pp.10-18
• /
• 1992

This paper considers and implementation of the memory system which provides simultaneous access to pq image points of block(p$\times$q), horizontal vector(1$\times$pq)and/vertical vector(pq$\times$1) in 2-dimension image array, where p and q are design parameters. This memory system consists of an address calculation circuit, address routing circuit, data routing circuit, module selection circuit and m memory modules where m>qp. The address calculation circuit computes pq addresses in parallel by using the difference of addresses among image points. Extra module assignment circuit is not used by improving module selection circuit with routhing circuit. By using Verilog-XL logic simulator, we verify the correctness of the memory system and estimate the performance. The implemented system provides simultaneous access to 16 image points and is 6 times faster than conventional memory system.

• Journal of information and communication convergence engineering
• /
• v.19 no.3
• /
• pp.175-179
• /
• 2021

Enhancing the reliability of the system is important for recent system-on-chip (SoC) designs. This importance has led to studies on fault diagnosis and tolerance. Fault-injection (FI) techniques are widely used to measure the fault-tolerance capabilities of resilient systems. FI techniques suffer from limitations in relation to environmental conditions and system features. Moreover, a hardware-based FI can cause permanent damage to the target system, because the actual circuit cannot be restored. Accordingly, we propose a simulation-based FI framework based on the Verilog Procedural Interface for measuring the failure rates of SoCs caused by soft errors. We execute five benchmark programs using an ARM Cortex M0 processor and inject soft errors using the proposed framework. The experiment has a 95% confidence level with a ±2.53% error, and confirms the reliability and feasibility of using proposed framework for fault analysis in SoCs.