• 제목/요약/키워드: System-on-Chip

검색결과 1,730건 처리시간 0.034초

Hysteresis-free organic field-effect transistors with ahigh dielectric strength cross-linked polyacrylate copolymer gate insulator

  • Xu, Wentao;Lim, Sang-Hoon;Rhee, Shi-Woo
    • 한국재료학회:학술대회논문집
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    • 한국재료학회 2009년도 추계학술발표대회
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    • pp.48.1-48.1
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    • 2009
  • Performance of organic field-effect transistors (OFETs) with various temperature-cured polyacrylate(PA) copolymer as a gate insulator was studied. The PA thin film, which was cured at an optimized temperature, showed high dielectric strength (>7 MV/cm), low leakage current density ($5{\times}10^{-9}\;A/cm^2$ at 1 MV/cm) and enabled negligible hysteresis in MIS capacitor and OFET. A field-effect mobility of ${\sim}0.6\;cm^2/V\;s$, on/off current ratio (Ion/Ioff) of ${\sim}10^5$ and inverse subthreshold slope (SS) as low as 1.22 V/decwere achieved. The high dielectric strength made it possible to scale down the thickness of dielectric, and low-voltage operation of -5 V was successfully realized. The chemical changes were monitored by FT-IR. The morphology and microstructure of the pentacene layer grown on PA dielectrics were also investigated and correlated with OFET device performance.

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시드 누적 순차적 추정 기법을 이용한 낮은 신호대잡음비 환경에서의 의사 잡음 부호 획득 (PN Code Acquisition at Low Signal-to-Noise Ratio Based on Seed Accumulating Sequential Estimation)

  • 윤석호;김선용
    • 한국통신학회논문지
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    • 제28권9A호
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    • pp.678-683
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    • 2003
  • Ward에 의해 제안된 순차적 추정에 기반을 둔 의사 잡음 부호 획득 방법은 비교적높은 신호대잡음비 환경에서는 우수한 성능을 보이지만, 낮은 신호대잡음비 환경에서는 그 성능이 크게 저하된다. 본 논문에서는 부호 획득에서 실제적으로 관심을 두고 있는 낮은 신호대잡음비 환경에서도 우수한 성능을 지니는 시드 누적 순차적 추정기법과 이에 기반을 둔 부호 획득 시스템을 제안하고, 제안한 시스템의 평균 획득 시간 성능을 분석한다. 제안한 시드 누적 순차적 추정 기법을 이용한 부호 획득 시스템은 기존의 순차적 추정 기법을 이용한 부호 획득 시스템에 비해 낮은 신호대잡음비 환경에서 매우 우수한 성능을 지니며, 그 성능향상의 정도가 의사 잡음 부호의 주기가 증가할수록 더 커짐을 보인다.

칩 온 필름을 위한 자동 결함 검출 시스템 개발 (Development of Automatic Fault Detection System for Chip-On-Film)

  • 류지열;노석호
    • 한국정보통신학회논문지
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    • 제16권2호
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    • pp.313-318
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    • 2012
  • 본 논문에서는 $30{\mu}m$ 이하의 초 미세 피치를 가진 칩 온 필름(chip-on-film, COF)에서 자주 발생하는 결함을 자동으로 검출할 수 있는 시스템을 제안한다. 개발된 시스템은 초 미세 패턴의 개방 및 단락 결함 뿐만아니라 소프트 개방 및 소프트 단락을 신속히 검출할 수 있는 회로 및 기술이 적용되어 있다. 결함 검출의 기본 원리는 결함 전의 패턴 저항값과 결함 후의 패턴 저항값 차에 의해 발생하는 미세 차동 전압을 읽어서 결함 유무를 판단한다. 또한 미세전압 차를 증폭시켜 결함 유무를 쉽게 판단할 수 있도록 고주파 공진기를 이용한다. 제안된 시스템은 초미세 패턴 COF 검사 과정에서 발생하는 다양한 결함을 신속하고 정확히 검출할 수 있으므로 기존의 COF 검사 시스템의 대안이 될 것으로 기대한다.

Monitoring system of physical behavior for dementia patient

  • Tanaka, Motohiro;Murakami, Ryuya;Dong, Rue Shao;Ishimatsu, Takakazu
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2003년도 ICCAS
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    • pp.1968-1970
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    • 2003
  • In this paper we propose a system to forecast the dangerous behavior of the dementia patients. Basic idea of our approach is to measure the body movements of the dementia patients using the acceleration sensor. Based on the data measured, warning the care-givers about possible dangerous actions like falling down from the bed and slipping down onto the floor to some extent. The signals measured by the acceleration sensor are processed by a one-chip computer. Based on the diagnosis of the one-chip computer , alert signal is generated to the care-giver by a wire-less signal. The sensor is implemented in a compact body . Applicability of the system is now being examined at a nursing home.

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플립칩 패키지에서 무연 솔더 조인트 및 UBM의 열충격 특성 해석 (An Analysis on the Thermal Shock Characteristics of Pb-free Solder Joints and UBM in Flip Chip Packages)

  • 신기훈;김형태;장동영
    • 한국공작기계학회논문집
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    • 제16권5호
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    • pp.134-139
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    • 2007
  • This paper presents a computer-based analysis on the thermal shock characteristics of Pb-free solder joints and UBM in flip chip assemblies. Among four types of popular UBM systems, TiW/Cu system with 95.5Sn-3.9Ag-0.6Cu solder joints was chosen for simulation. A simple 3D finite element model was first created only including silicon die, mixture between underfill and solder joints, and substrate. The displacements due to CTE mismatch between silicon die and substrate was then obtained through FE analysis. Finally, the obtained displacements were applied as mechanical loads to the whole 2D FE model and the characteristics of flip chip assemblies were analyzed. In addition, based on the hyperbolic sine law, the accumulated creep strain of Pb-free solder joints was calculated to predict the fatigue life of flip chip assemblies under thermal shock environments. The proposed method for fatigue life prediction will be evaluated through the cross check of the test results in the future work.

횡방향 열초음파 본딩 기법을 이용한 COG 접합 (Chip on Glass Interconnection using Lateral Thermosonic Bonding Technology)

  • 하창완;윤원수;박금생;김경수
    • 한국정밀공학회지
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    • 제27권7호
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    • pp.7-12
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    • 2010
  • In this paper, chip-on-glass(COG) interconnection with anisotropic conductive film(ACF) using lateral thermosonic bonding technology is considered. In general, thermo-compression bonding which is used in practice for flip-chip bonding suffers from the low productivity due to the long bonding time. It will be shown that the bonding time can be improved by using lateral thermosonic bonding in which lateral ultrasonic vibration together with thermo-compression is utilized. By measuring the internal temperature of ACF, the fast curing of ACF thanks to lateral ultrasonic vibration will be verified. Moreover, to prove the reliability of the lateral thermosonic bonding, observation of pressured mark by conductive particles, shear test, and water absorption test will be conducted.

X선 영상의 에지 추출을 통한 플립칩 솔더범프의 접합 형상 오차 검출 (Detection of Flip-chip Bonding Error Through Edge Size Extraction of X-ray Image)

  • 송춘삼;조성만;김준현;김주현;김민영;김종형
    • 제어로봇시스템학회논문지
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    • 제15권9호
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    • pp.916-921
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    • 2009
  • The technology to inspect and measure an inner structure of micro parts has become an important tool in the semi-conductor industrial field with the development of automation and precision manufacturing. Especially, the inspection skill on the inside of highly integrated electronic device becomes a key role in detecting defects of a completely assembled product. X-ray inspection technology has been focused as a main method to inspect the inside structure. However, there has been insufficient research done on the customized inspection technology for the flip-chip assembly due to the interior connecting part of flip chip which connects the die and PCB electrically through balls positioned on the die. In this study, therefore, it is implemented to detect shape error of flip chip bonding without damaging chips using an x-ray inspection system. At this time, it is able to monitor the solder bump shape by introducing an edge-extracting algorithm (exponential approximation function) according to the attenuating characteristic and detect shape error compared with CAD data. Additionally, the bonding error of solder bumps is automatically detectable by acquiring numerical size information at the extracted solder bump edges.

DSP 기반 통신 소프트웨어의 설계 및 테스트베드 (Design of Communication Software Based on DSP and Implementation of Testbed)

  • 황택규
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1999년도 하계종합학술대회 논문집
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    • pp.1137-1140
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    • 1999
  • In this thesis, we research about Communication System Construction and Test-Bed Realization Method and Software’s Design with written program into Embedded Micro Controller’s restricted memory region using a DSP Chip to deal with mainly high speed communication. Tools used for modern communication network control use TI or AMD general chip class, but nevertheless responsibility for the point at issue, Analog Device is architecture design model moderated for small communication system. In this thesis, we present extended model, and realize basic case.

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VHDL을 이용한 서보시스템의 공간벡터 변조부 설계 (Design of the Space Vector Modulation of Servo System using VHDL)

  • 황정원;박승엽
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2001년도 하계종합학술대회 논문집(5)
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    • pp.5-8
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    • 2001
  • In this paper, we have space vector PWM(Pulse Width Modulation) circuits on the FPGA(Field Programmable Gate Arry) chip designed by VHDL(Very high speed integrated circuit Hardware Description Language). This circuit parts was required at controlling the AC servo motor system and should have been designed with many discrete digital logics. In the result of this study, peripheral circuits are to be simple and the designed logic terms are robust and precise. Because of it's easy verification and implementation, we could deduced that the customize FPGA chip show better performance than that of circuit modules parts constituted of discrete IC.

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An On-Chip Differential Inductor and Its Use to RF VCO for 2 GHz Applications

  • Cho, Je-Kwang;Nah, Kyung-Suc;Park, Byeong-Ha
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제4권2호
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    • pp.83-87
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    • 2004
  • Phase noise performance and current consumption of Radio Frequency (RF) Voltage-Controlled Oscillator (VCO) are largely dependent on the Quality (Q) factor of inductor-capacitor (LC) tank. Because the Q-factor of LC tank is determined by on-chip spiral inductor, we designed, analyzed, and modeled on-chip differential inductor to enhance differential Q-factor, reduce current consumption and save silicon area. The simulated inductance is 3.3 nH and Q-factor is 15 at 2 GHz. Self-resonance frequency is as high as 13 GHz. To verify its use to RF applications, we designed 2 GHz differential LC VCO. The measurement result of phase noise is -112 dBc/Hz at an offset frequency of 100 kHz from a 2GHz carrier frequency. Tuning range is about 500 MHz (25%), and current consumption varies from 5mA to 8.4 mA using bias control technique. Implemented in $0.35-{\mu}m$ SiGe BiCMOS technology, the VCO occupies $400\;um{\times}800\;um$ of silicon area.