• Journal of Sensor Science and Technology
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• v.6 no.2
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• pp.115-122
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• 1997

In this paper, on-chp atomatic tuning circuit, using proposed integration level approximation technique, is designed to tuning of the variation of RC time-constant due to aging or temperature variation, etc. This circuit reduces the error, the difference between code values and real outputs of integrator, which is drawback of presented dual-slope tuning circuit and eliminates modulations of processing signals in integrated circuit due to fixed tuning codes during ordinary operation. This system is made up of simple integrator, A/D converter and digital control circuit and all capacitors are replaced by programed capacitor arrays in this system. This tuning circuit with 4 bit resolution achieves $-9.74{\sim}+9.68%$ of RC time constant error for 50% resistance variation.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.6
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• pp.324-332
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• 2005

In general, bus system consumes a very significant portion of power in a chip. Bus splitting can be used to reduce the energy dissipation and to reduce the Propagation delay on the bus by lowering the parasitic load of each bus segment. Data exchange probability distribution between a set of interconnected processing elements affects the average energy dissipation of the splitted bus architectures. In this research, we have developed tree-based bus splitting techniques and design methodologies, as an extension of horizontally aligned bus splitting. We have developed the methodology to select near-optimal bus architectures for low energy dissipation when data exchange probability distribution of a system is given. Experimental results show that the proposed techniques can reduce energy dissipation on the bus by up to 83$\%$.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.4
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• pp.285-292
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• 2007

SoC which deploys software modules as well as hardware IPs on a single chip is a major revolution taking place in the implementation of a system design, and high-level synthesis is an important process of SoC design methodology. Recently, SPARK parallelizing high-level synthesis software tool has been developed. It takes a behavioral ANSI-C code as an input, schedules it using code motion and various code transformations, and then finally generates synthesizable RTL VHDL code. Although SPARK employs various loop transformation algorithms, the synthesis results generated by SPARK are not acceptable for basic signal and image processing algorithms with nested loop. In this paper we propose a SoC platform with an application-specific PLD targeting local operations which are feature of many loop algorithms used in signal and image processing, and demonstrate design process which maps behavioral specification with nested loops written in a high-level language (ANSI-C) onto 2D systolic array. Finally the derived systolic array is implemented on the proposed application-specific PLD of SoC platform.

• Journal of the Korea Society of Computer and Information
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• v.13 no.6
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• pp.33-39
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• 2008

Energy efficiency should be considered together with performance when designing embedded processors. This paper proposes a new energy-aware instruction cache design using backward branch information to reduce the energy consumption in an embedded processor, since instruction caches consume a significant fraction of the on-chip energy. Proposed instruction cache is composed of two caches: a large main instruction cache and a small loop instruction cache. Proposed technique enables the selective access between the main instruction cache and the loop instruction cache to reduce the number of accesses to the main instruction cache, leading to good energy efficiency. Analysis results show that the proposed instruction cache reduces the energy consumption by 20% on the average, compared to the traditional instruction cache.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.2
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• pp.273-280
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• 2017

As massive integration technology of transistors has been developing, multi-core circuit is fabricated on a silicon chip and a clock frequency is getting faster to meet the system requirement. But increasing the clock frequency can induce some problems to violate the operation of system such as clock synchronization, so it is very import to avoid metastability events to design digital chips. In this paper, metastability windows are measured by bisection method in H-spice depending on temperature, supply voltage, and the size of transmission gate with D-FF designed with 180nm CMOS process. The simulation results show that the metastability window(: MW) is slightly increasing to temperature and supply voltage, but is quadratic to the area of a transmission gate, and the best area ration of P and Ntransitor in transmission gate is P/N=4/2 to get the least MW.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2628-2635
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• 2010

This paper analyzes the detection probability of FMCW (Frequency Modulated Continuous Wave) radar based on Doppler frequency and analog-digital converter bit and designs and implements signal processing part of FMCW radar. For performance evaluation, the FMCW radar system consists of a transmitted part and a received part and uses AWGN channel. The system model is verified through analysis and simulation. Frequency offset occurs in the received part caused by the mismatching between the received signal and the reference signal. In case of Doppler frequency less than about 38KHz, performance degradation of detection does not occur in FMCW radar with 75cm resolution The analog-digital converter needs at least 6 bit in order not to degrade the detection probability. And, we design and implement digital signal processing part based on DDS chip of digital transmitted signal generator for FMCW radar.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1645-1646
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• 2006

Micro ElectroMechanical Systems (MEMS) 기술을 이용한 초미세 유체 제어 시스템 (마이크로 펌프, 마이크로 밸브, 마이크로 채널, 마이크로 믹서 등)은 화학, 생명분야의 DNA 분석, 항원-항체 분석, 질병의 진단 등에 사용되는 lab-on-a-chip, micro total analysis system ($\mu$-TAS) 등에서 화학 및 바이오 유체를 제어하는 분석 시스템의 일부분으로서 사용되며 필수적으로 요구된다. 본 논문에서는 이러한 microchip을 구현하기 위해 초미세 유체 제어 소자인 마이크로 펌프와 밸브를 같은 기관 위에 polydimethylsiloxane (PDMS)와 indium tin oxide (ITO)-Glass를 사용하여 동일한 구조로 집적 하였다. 마이크로 펌프의 pumping rate은 인가 직류 펄스 전력의 주파수와 duty 비를 변화시켜 최적화하였다. 직류 펄스 전력 500 mW를 인가하였을 때 주파수 2 Hz, duty 비 7 %에서 약 $1.05{\mu}l/min$의 최대 유량이 측정되었다. 마이크로 밸브는 ITO 히터에 전력을 인가함으로서 유량의 on/off 제어가 잘 됨을 확인할 수 있었고 유체를 closing하기 위해 필요한 전력은 약 300 mW이다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.10
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• pp.849-856
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• 2012

Chip on board type white light emitting diode on metal core printed circuit board with high thixotropy silicone is fabricated by vacuum printing encapsulation system. Encapsulant is chosen by taking into account experimental results from differential scanning calorimeter, shearing strength, and optical transmittance. We have observed that radiant flux and package efficacy are increased from 336 mW to 450 mW and from 11.9 lm/W to 36.2 lm/W as single dome diameter is varied from 2.2 mm to 2.8 mm, respectively. Double encapsulation structure with 2.8 mm of dome diameter shows further significant enhancement of radiant flux and package efficacy to 667 mW and 52.4 lm/W, which are 417 mW and 34.8 lm/W at single encapsulation structure, respectively.

• Journal of Astronomy and Space Sciences
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• v.19 no.4
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• pp.327-340
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• 2002

In this paper, we performed the design study of a wide-band digital autocorrelation spectrometer for the observation study of an extra-galaxy's spectral lines and the survey research of the special radio sources in field of the radio astronomy observational research. The autocorrelation spectrometer designed in this paper can be used to their spectrometer of any system because this spectrometer has a wide dynamic power and frequency range properties. In this system we use the aliasing sampling method to minimize the band loss. For the output signal of the correlator we can increase the signal processing speed using by a special DSP chip, the integration and the FFT using hardware, so this spectrometer can support the newest developed technique for the radio astronomy observation so called “On the fly” method.

• The KIPS Transactions:PartA
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• v.16A no.2
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• pp.79-88
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• 2009

In boundary scan architecture, test stimuli are shifted in one at a time and applied to the on-chip system logic. The test results are captured into the BSR and are examined by subsequent shifting. In this paper, we developed a continuous capture test architecture and test procedure using TPG based on boundary scan is used to performance test. In this architecture, test patterns of TPG are applied to CUT with system clock rate, and response of CUT is continuously captured by CBSR(Continuous Capture Boundary Scan Register) at the same rate and the captured results is shifted to TDO at the same rate. The suggested a continuous capture test architecture and test procedure is simulated by Altera Max+Plus 10.0. The simulation results shows the accurate operation and effectiveness of the proposed test architecture and procedure.