• 제어로봇시스템학회논문지
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• 제14권8호
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• pp.824-836
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• 2008

Relaxed static stability(RSS) concept has been applied to improve aerodynamic performance of modern version supersonic jet fighter aircraft. Therefore, flight control systems are necessary to stabilize an unstable aircraft, and provides adequate handling qualities and achieve performance enhancements. Standard FCSDVP (Flight Control System Design and Verification Process) is provided to reduce development period of the flight control system. In addition, if this process is employed in developing flight control system, it reduces the trial and error for development and verification of flight control system. This paper addresses the flight control system design and verification process for the RSS aircraft utilizing design goal based on military specifications, linear and nonlinear system design and verification based on universal software, handling quality test based on HILS(Hardware In-the-Loop Simulator) environment, and ground and flight test results to verify aircraft dynamic flight responses.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2009년도 춘계학술대회 논문집
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• pp.483-494
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• 2009

Since the embedded system is more intelligent, the importance of the reliability in the embedded system is a lot more visible. Especially the reliability of the embedded system in the train control system is even better important. As the special quality of the embedded system, the hardware of the system is directly controlled by the software in the embedded system. As the expansion of complexity, the expense amd the time for verification is required more and more. This paper is presented the verification of the reliability as the method with background of failure Embedded system is gradually, the importance of 'A built-in on the system embedded system's reliability is focused. In particular, in the train control system built-in of the embedded system, reliability is even more important. The embedded system of the system controls over hardware, software with built-in directly. The more complex system is, the more increasable of depending on the reliability of the time verification and expensive is. This paper is about he characteristics of the reliability and verification of embedded system under the failure mechanisms, based on the verification methodology suggested by in the train control system.

• 대한기계학회논문집A
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• 제30권7호
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• pp.816-825
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• 2006

This paper describes the development of a web-based interference verification system in the mold design process. Although several commercial CAD systems furnish interference verification functions, those systems are very expensive and inadequate to perform collaborative works over the Internet. In this paper, an efficient and precision hybrid interference verification algorithm for the web-based interference verification system over the distributed environment has been studied. The proposed system uses lightweight CAD files produced from the optimally transformed CAD data through ACIS kernel and InterOp. Collaborators related to the development of a new product are able to verify the interference verification over the Internet without commercial CAD systems. The system reduces production cost, errors and lead-time to the market. Validity of the developed system is confirmed through case studies.

• 무역상무연구
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• 제58권
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• pp.267-286
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• 2013

Origin verification is regarded most essential for FTA performance administration. This administration is divided into direct and indirect system where Korea has adapted indirect system to Korea-EU FTA while direct system to Korea-USA FTA. A comparative analysis was conducted on the system of origin verification and provisions contained in preferential tariff law of each countries. The study finds that Korean origin verification system is a bit lack of procedural provision resulting in less protection of domestic trader's rights. Another point is that Korean Customs Authority is weak, in respect of organization and man power, to protect illegal bilateral tariff application by counter part FTA countries. And therefore this study suggests the policy makers to arrange detailed FTA origin verification procedures with earliest meeting with counter part FTA countries, and further stress that make up of organization and man power for origin verification in a timely manner.

• 반도체디스플레이기술학회지
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• 제23권1호
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• pp.25-35
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• 2024

In the present modern day, as the complexity and size of SoC(System on Chip) increase, the importance of design verification are increasing, Therefore it takes a lot of time to verify the design. There is an emerging need to manage the verification environment faster and more efficiently by reusing the existing verification environment. UVM-based verification is a standardized and highly reliable verification method widely adopted and used in the semiconductor industry. This paper presents a UVM-based verification for the 4 tap equalizer module with a systolic array structure. Through the constraints randomization, it was confirmed that various test scenarios stimulus were generated. In addition, by verifying a simulation comparing the actual DUT outputs with the MATLAB reference outputs, the reuse and efficiency of the UVM test bench could be confirmed.

• 융합신호처리학회논문지
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• 제10권4호
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• pp.274-279
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• 2009

시스템수준 설계방법론에서 널리 사용하고 있는 설계흐름도는 시스템명세, 시스템수준의 HW/SW 분할, HW/SW 통합설계, 가상 또는 물리적 프로토타입을 이용한 통합검증, 시스템통합으로 구성된다. 본 논문에서는 SystemVerilog와 SystemC를 기반으로 하여 신속한 기능검증이 가능한 native-code 통합검증환경과 클럭수준 검증까지 가능한 계층화 통합검증환경을 각각 구현하였다. Native-code 통합검증환경은 시스템수준 설계언어인 SystemC를 이용하여 HW/SW 분할단계를 수행한 후, SoC 설계의 HW부분과 SW부분을 각각 SystemVerilog와 SystemC로 모델링하여 상호작용을 하나의 시뮬레이션 프로세스로 검증한다. 계층화된 SystemVerilog 테스트벤치는 임의의 테스트벡터를 생성하여 DUT의 모서리 시험을 포함하는 검증환경으로 본 논문에서는 SystemC를 도입하여 다중 상속을 가지는 통합검증환경의 구성요소를 먼저 설계한 후, SystemVerilog DPI와 ModelSim 매크로를 이용하여 SystemVerilog 테스트벤치와 결합된 통합검증환경을 설계한다. 다중 상속은 여러 기초클래스를 결합한 새로운 클래스를 정의하여 코드의 재사용성을 높이는 장점을 가지므로, 본 논문의 SystemC를 도입한 통합검증환경 설계는 검증된 기존의 코드를 재사용할 수 있는 이점을 가진다.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 2003년도 ISIS 2003
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• pp.216-219
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• 2003

Among the techniques to protect private information by adopting biometrics, speaker verification is expected to be widely used due to advantages in convenient usage and inexpensive implementation cost Speaker verification should achieve a high degree of the reliability in the verification nout the flexibility in speech text usage, and the efficiency in verification system complexity. Continuants have excellent speaker-discriminant power and the modest number of phonemes in the category, and multilayer perceptrons (MLPs) have superior recognition ability and fast operation speed. In consequence, the two provide viable ways for speaker verification system to obtain the above properties. This paper implements a system to which continuants and MLPs are applied, and evaluates the system using a Korean speech database. The results of the experiment prove that continuants and MLPs enable the system to acquire the three properties.

• 융합신호처리학회논문지
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• 제12권2호
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• pp.145-149
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• 2011

최근 시스템의 규모가 커지고 복잡해지면서, 시스템 수준에서의 기능 검증방법론이 중요해지고 있다. 기능블록의 검증을 위해서는 주로 BFM(bus functional model)이 사용되며, 기능 검증에 대한 부담이 증가할수록 올바른 검증환경 구성의 중요성은 더욱 증가한다. SystemVerilog는 Verilog HDL의 확장으로 하드웨어 설계언어의 특징과 검증언어의 특징을 동시에 갖는다. 동일한 언어로 설계기술, 기능 시뮬레이션 그리고 검증을 진행할 수 있다는 것은 시스템개발에서 큰 이점을 갖는다. 본 논문에서는 SystemVerilog를 이용하여 AMBA 버스와 기능블록으로 구성된 DUT를 설계하고, 계층적 테스트벤치를 이용한 검증환경에서 DUT의 가능을 검증한다. 기능 블록은 Adaptive FIR 필터와 Booth's 곱셈기를 사용한다. 이를 통하여 검증환경이 DUT와 연결되는 인터페이스의 부분적인 변경을 통하여 다른 하드웨어의 기능을 검증하는데 재사용되는 이점을 가지고 있음을 확인한다.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2010년도 춘계학술대회 논문집
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• pp.1821-1828
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• 2010

In this study we suggest a method of optimization of verification hierarchy structure and system requirements management by using a verification matrix with traceability consideration. Verification items were gathered in the process of CDR(Critical Design Review), and analyzed with respect to requirements traceability structure. Missed or overlapped items were adjusted, and cross-correlated items between sub-systems were clustered and rearranged in order to structurize verification requrements (VRs). Those VRs are to be used as a guideline for the test and evaluation planning, development of test items and procedure, and system requirements management throughout the system integration stages.

• 한국통신학회논문지
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• 제34권3C호
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• pp.257-267
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• 2009

This paper presents a training method for neural networks and the employment of MSE (mean scare error) values as the basis of a decision regarding the identity claim of a speaker in a recurrent neural networks based speaker verification system. Recurrent neural networks (RNNs) are employed to capture temporally dynamic characteristics of speech signal. In the process of supervised learning for RNNs, target outputs are automatically generated and the generated target outputs are made to represent the temporal variation of input speech sounds. To increase the capability of discriminating between the true speaker and an impostor, a discriminative training method for RNNs is presented. This paper shows the use and the effectiveness of the MSE value, which is obtained from the Euclidean distance between the target outputs and the outputs of networks for test speech sounds of a speaker, as the basis of speaker verification. In terms of equal error rates, results of experiments, which have been performed using the Korean speech database, show that the proposed speaker verification system exhibits better performance than a conventional hidden Markov model based speaker verification system.