• Proceedings of the Korea Information Processing Society Conference
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• 2014.11a
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• pp.53-56
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• 2014

Application specific instruction-set processor (ASIP) is a suitable design choice for system designers who seek both flexibility to handle various applications in the domain together with the performance. Successful development of an ASIP, however, requires a software development kit (SDK) to be provided along with the processor. Synopsys Processor Designer is an ASIP development tool, which takes as input a set of files written in a high-level architecture description language called LISA (Language for Instruction Set Architecture), and generates SDK as well as RTL. Recently, they have added support for the generation of LLVM compiler backend, though some manual work is required. In this paper, we introduce some details in porting LLVM compiler to a custom processor architecture in Synopsys Processor Designer.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2002.06a
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• pp.87-87
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• 2002

본 논문에서는 모듈성과 확장성을 갖는 시스톨릭 어레이 정렬기(Systolic Array Sorter)의 구현에 대하여 기술한다. 정규순환방정식으로 표현된 정렬(sorting)알고리즘으로부터 1차원 평면 시스톨릭 어레이를 유도한 후 유도된 정렬 시스톨릭 어레이를 RTL 수준에서 VHDL로 모델링 하여 동작을 검증하였다. 검증된 시스톨릭 어레이 정렬기는 synopsys hynix-0.35$\mu\textrm{m}$ 셀 라이브러리와 FPGA s40pq240칩을 사용하여 합성 및 구현되었다.

• Journal of the Korea Society of Computer and Information
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• v.8 no.2
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• pp.112-121
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• 2003

Information Protection and cryptography technology is developed with if but solved problem of real time processing and secret maintain. Therefore this paper is Proposed new PRN-SEED(Pseudo-Random Number-SEED) for the increasing secret rate and processing rate perform performance analysis with existed other cryptography algorithms. Proposed new PRN-SEED crypto-algorithm increase in the processing rate than existed algorithms use bit and byte mixed operation with RNG(Random Number Generator). PRN-SEED that performs simultaneous operations have higher 1.03 in the processing rate and 2 in the cryptosystem performance than existed cryptosystems. Implementation for PRN-SEED use Synopsys Design Analyser Ver. 1999.10, samsung KG75 library and Synopsys VHDL Debegger. As a simulation result, symmetric cryptosystem DES operate 416Mbps at the 40MHz and Rijndael operate 612Mbps at the 50MHz. PRN-SEED cryptosystem have gate counting 10K and operate 430Mbps at the 40MHz and 630Mbps at the 50MHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.251-263
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• 2008

In this paper, we report an analytical modeling and 2-D Synopsys Sentaurus TCAD simulation of ion implanted silicon carbide MESFETs. The model has been developed to obtain the threshold voltage, drain-source current, intrinsic parameters such as, gate capacitance, drain-source resistance and transconductance considering different fabrication parameters such as ion dose, ion energy, ion range and annealing effect parameters. The model is useful in determining the ion implantation fabrication parameters from the optimization of the active implanted channel thickness for different ion doses resulting in the desired pinch off voltage needed for high drain current and high breakdown voltage. The drain current of approximately 10 A obtained from the analytical model agrees well with that of the Synopsys Sentaurus TCAD simulation and the breakdown voltage approximately 85 V obtained from the TCAD simulation agrees well with published experimental results. The gate-to-source capacitance and gate-to-drain capacitance, drain-source resistance and trans-conductance were studied to understand the device frequency response. Cut off and maximum frequencies of approximately 10 GHz and 29 GHz respectively were obtained from Sentaurus TCAD and verified by the Smith's chart.

• The Magazine of the IEIE
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• v.41 no.11
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• pp.58-66
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• 2014

• The Optical Journal
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• s.177
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• pp.56-57
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• 2020

• The Optical Journal
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• s.176
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• pp.20-21
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• 2020

• Journal of Korea Multimedia Society
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• v.4 no.3
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• pp.222-229
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• 2001

Many techniques have been proposed for digital image enlargement, which use spatially neighbored pixels information in a still image. In this paper, we propose the digital image interpolation method that improves edge characteristics by selectively transposing the sub-windows of pseudomedian filter, which results in relatively better performance than others. We have simulated the proposed algorithm using Visual C++ and verified performance of the algorithm by PSNR(Peak signal Noise Ratio) and edge characteristics. Finally, we have designed the adaptive pseudomedian by using synopsys VHDL(Very high speed integrated circuit Hardware Description Language).

• The Journal of the Acoustical Society of Korea
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• v.18 no.1
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• pp.45-52
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• 1999

In this thesis, a packer is proposed and designed for removing the bottle-neck effect and easy signal processing using a new algorithm with the operation frequency of 54MHz. To verify the performance of the proposed packer, DCT coefficient encoding block with ROM table using a combinational logic is designed and its output data are used the input data of the packer. Circuits in this thesis are designed by using VHDL code and its modeling and simulation are performed by SYNOPSYS tool using $0.65{\mu}m$ rule.

• Journal of the Korean Institute of Intelligent Systems
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• v.10 no.5
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• pp.478-486
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• 2000

This paper proposes a design method that can minimize the power dissipation of CMOS digital circuits without affecting their optimal operation speeds. The proposed method is based on genetic algorithms(GAs) combined to the retiming technique, a circuit transformation technique of repositioning flip-flops. The proposed design method consists of two phases: the phase of retiming for optimizing clock periods and the phase of GA retiming for minimizing power dissipation. Experimental results using Synopsys Design Analyzer show that the proposed design method can reduce the critical path delay of example circuits by about 30-50% and improve the dynamic power performance of the circuits by about 1.4~18.4%.