• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.6
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• pp.51-57
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• 2017

In this paper, we designed a frequency synthesizer using DDS (Direct Digital Synthesizer) for Ka-band compact Radar. DDS is applied to generate various waveform and to cover high-speed frequency sweep. In order to reduce size, waveform generator and Ka band frequency up-converter are integrated in one module. Proposed frequency synthesizer provides LFM(Linear Frequency Modulation) waveform and Phase modulated FMCW (Frequency Modulation Continuous Wave) waveform. It is observed that fabricated synthesizer performs $0.191{\mu}sec$ frequency switching time and -89.16 dBc/Hz phase noise at offset 1 kHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.70-79
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• 2016

This paper proposes a low-power range-scaled 14b 30 MS/s pipeline-SAR composite ADC for high-performance CIS applications. The SAR ADC is employed in the first stage to alleviate a sampling-time mismatch as observed in the conventional SHA-free architecture. A range-scaling technique processes a wide input range of 3.0VP-P without thick-gate-oxide transistors under a 1.8 V supply voltage. The first- and second-stage MDACs share a single amplifier to reduce power consumption and chip area. Moreover, two separate reference voltage drivers for the first-stage SAR ADC and the remaining pipeline stages reduce a reference voltage disturbance caused by the high-speed switching noise from the SAR ADC. The measured DNL and INL of the prototype ADC in a $0.18{\mu}m$ CMOS are within 0.88 LSB and 3.28 LSB, respectively. The ADC shows a maximum SNDR of 65.4 dB and SFDR of 78.9 dB at 30 MS/s, respectively. The ADC with an active die area of $1.43mm^2$ consumes 20.5 mW at a 1.8 V supply voltage and 30 MS/s, which corresponds to a figure-of-merit (FOM) of 0.45 pJ/conversion-step.

• Journal of Advanced Marine Engineering and Technology
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• v.17 no.5
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• pp.71-85
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• 1993

The Cycloconverter that the author is going to treat in this paper, has strong advantages over the D.C. Link Inverter in points of chattering torque problem and natural commutation. Thus, the Cycloconverter is expected to be well applied to large and low-speed machines which require better speed control at low frequency. But the control circuit of Cycloconverter has two weak points described as follows. 1) Because of its rather complicated control circuit, it is likely to be illoperating due to unexpected noise signals, thus the higher the accuracy and reliability of the circuit is required to be, the more the circuit may cost. 2) Because the load current is not purely sinusoidal, the Cycloconverter may possibly be destroyed in case of inaccurate convert switching resulted from the difficulties in detecting the load current-zero and the current direction at the moment. In this paper, the author first of all intends to design and build a modified VVVF-type Noncirculating Current Cycloconverter to which recently proposed control methods are applied for improving the circuit simplicity, the control performance, and the system reliability. And then, experiments for observing the output waveforms of the Cycloconverter which is controlled by Singled-Board Computer using 8086 16-bit microprocesser are carried out. Finally the author concludes the result of this study as follows. 1) By replacing the conventional analog control circuits such as Reference Wave Generator, Cosine Timing Wave Generator, and Comparator with softwares, a great circuit simplicity is achieved. 2) The output of the designed Cycloconverter changes its frequency very fast without showing discontinuity of its waveform, and this waveform characteristics enables the smooth speed control of Induction Motor. 3) The design control circuit of Cycloconverter can be applied to the systems of 12 or 24 pulses because of its short processing period.

• The KIPS Transactions:PartC
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• v.9C no.4
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• pp.581-588
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• 2002

In this paper, we newly propose the optical CDMA routing scheme for the radio access network. At the radio base station (RBS), the received radio signals are multiplied by the PN codes and converted to the CDMA radio signals. In the next optical CDMAS are performed and multiplxed by using the PN codes which are the addresses of the routing mobile switching center (MSC). At the MSC, the CDMA radio signals are routined to another MSC by the CDM receiver at the routing node. In the case MSC is equal to the desired MSC, the radio signal is correlated by the two-layerd spectrum despreading at a time. Finally we theoretically analyze the signal-to-interference and noise power ratio of regenerated signal and the routing error probability and show the availability of proposed scheme.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.10
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• pp.5105-5114
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• 2013

This paper is conducted a research of the cable and filter design considering the deep sea floor environment. The electric architecture which is being used in the subsea plant is comprised of the power supply unit of the high voltage, high-capacity drive system, long cable, and electric motor in the sea area. Conducted emission is occurred by the rapid voltage change at the moment of switching at high speed of inverter for driving motors. The more the length of the cable is lengthened, the worse the motor is influenced by transient voltage. Thus, the over voltage occurred in the drive motor was confirmed by designed wire which is considered R, L, line-to-line C, line-to-gnd C of long cable used in the subsea plant. A guide line of the subsea plant model is also suggested by using a filter to reduce conducted noise of PWM inverter drive-system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.69-75
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• 2004

This work proposes an 8b 220 MS/s 230 mW 3-stage pipeline CMOS ADC with on-chip filers for temperature- and power- insensitive voltage references. The proposed RC low-pass filters improve switching noise performance and reduce reference settling time at heavy R & C loads without conventional off-chip large bypass capacitors. The prototype ABC fabricated in a 0.25 um CMOS occupies the active die area of 2.25 $\textrm{mm}^2$ and shows the measured DNL and INL of maximum 0.43 LSB and 0.82 LSB, respectively. The ADC maintains the SNDR of 43 dB and 41 dB up to the 110 MHz input at 200 MS/s and 220 MS/s, respectively, while the SNDR at the 500 MHz input is degraded as much as only 3 dB than the SNDR at the 110 MHz input.

• Journal of electromagnetic engineering and science
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• v.11 no.4
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• pp.282-289
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• 2011

GHz electromagnetic interference (EMI) characteristics are analyzed for a 3dimensional (3D) stacked chip power distribution network (PDN) with through silicon via (TSV) connections. The EMI problem is mostly raised by P/G (power/ground) noise due to high switching current magnitudes and high PDN impedances. The 3D stacked chip PDN is decomposed into P/G TSVs and vertically stacked capacitive chip PDNs. The TSV inductances combine with the chip PDN capacitances produce resonances and increase the PDN impedance level in the GHz frequency range. These effects depend on stacking configurations and P/G TSV designs and are analyzed using the P/G TSV model and chip PDN model. When a small size chip PDN and a large size chip PDN are stacked, the small one's impedance is more seriously affected by TSV effects and shows higher levels. As a P/G TSV location is moved to a corner of the chip PDNs, larger PDN impedances appear. When P/G TSV numbers are enlarged, the TSV effects push the resonances to a higher frequency range. As a small size chip PDN is located closer to the center of a large size chip PDN, the TSV effects are enhanced.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.251-254
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• 2002

In the design of mobile wireless communication system, the location of BTS(Base Transciver Stations), RSC(Base Station Controllers), and MSC(Mobile Switching Center) is one of the most important parameters. Designing wireless communication system, the cost of equipment is need to be made low by combining various, complex parameters. We can solve this problem by combinatorial optimization algorithm, such as Simulated Annealing, Tabu Search, Genetic Algorithm, Random Walk Algorithm that have been extensively used for global optimization. This paper shows the four kind of algorithms which are applied to the location optimization of BTS, BSC, and MSC in designing mobile communication system and then we compare with these algorithms. And also we analyze the experimental results and shows the optimization process of these algorithms. As a the channel of a CDMA system is shared among several users, the receivers face the problem of multiple-access interference (MAI). Also, the multipath scenario leads to intersymbol interference (ISI). Both components are undesired, but unlike the additive noise process, which is usually completely unpredictable, their space-time structure helps to estimate and remove them.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.5
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• pp.843-850
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• 2016

In this paper, we propose a digital controller design process for the interleaved type of a boost PFC (Power Factor Correction) converter which can disperse the heat of the switching devices due to the interleaved topology. We establish a mathematical model of a boost PFC converter and propose a controller design method based on the root locus. The performance of the designed controller is verified by simulations. The measurement of the input voltage, inductor currents, and the converter output link voltage are needed for the control of the converter system which consists of a power unit and a control unit where a high-performance 32-bit microcontroller is used. The adjustment of A/D conversion timing is also needed to avoid high frequency noise generated when the switches on/off. It is illustrated by the real experiments that the designed control system with the properly adjusted ADC timing satisfies the given performance specifications of the interleaved boost PFC converter in the on-board slow battery charger.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.445-448
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• 2005

A new high efficiency phase shifted full bridge (PSFB) converter for sustaining power module of plasma display panel (PDP) is proposed in this paper .The proposed converter employs the rectifier of voltage doubler type without output inductor. Since it has no output inductor, the voltage stresses of the secondary rectifier diodes can be clamped at the level of the output voltage. Therefore, no dissipative resistor-capacitor (RC) snubber for rectifier diodes is needed and a high efficiency as well as low noise cutout voltage can be realized. In addition, due to elimination of the large output inductor, it features a simple structure, lower cost, less mass, and lighter weight. Furthermore, the proposed converter has wide zero voltage switching (ZVS ) ranges with low current stresses of the primary switches. Also the resonance between the leakage inductor of the transformer and the capacitor of the voltage doubler cell makes the current stresses of the primary switches and rectifier diodes reduced. In this paper, the operational principles, analysis of the proposed converter, and the experimental results are presented.