• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.15-22
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• 2006

In this paper, 1.8V 8-bit 500MSPS Low-power CMOS Digital-to-Analog Converter(DAC) for UWB(Ultra Wide Band) Communication Systeme is proposed. The architecture of the DAC is based on a current steering 6+2 full matrix type which has low glitch and high linearity. In order to achieve a high speed and good performance, a current cell with a high output impedance and wide swing output range is designed. Further a thermometer decoder with same delay time and low-power switching decoder for high efficiency performance are proposed. The proposed DAC was implemented with TSMC 0.18um 1-poly 6-metal N-well CMOS technology. The measured SFDR was 49dB when the output frequency was 50MHz at 500MS/s sampling frequency. The measured INL and DNL were 0.9LSB and 0.3LSB respectively. The DAC power dissipation was 20mW and the effective chip area was $0.63mm^2$.

• IE interfaces
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• v.4 no.1
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• pp.63-69
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• 1991

In this paper, the Go-Back-N ARQ protocol with decoding in communication network is considered. The time delay and throughput are respectively analyzed as a function of window size and decoding time out. Packets arrive continuously at the decoder, and are stored in a buffer if the decoder is busy upon its arrival. The decoder devotes no more than a time-out period of predetermined length to the decoding of any single packet. If packet decoding is completed within that period, the packet leaves the system. Otherwise, it is retransimitted and its decoding starts anew. The time delay and throughput are obtained using recursive formula and difference equation. An appropriate time out and window size that satisfies the grade of service can be determined.

• The KIPS Transactions:PartA
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• v.12A no.1 s.91
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• pp.1-6
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• 2005

This paper presents a new algorithm on low power survivor path memory implementation of the trace-back systolic array Viterbi algorithm. A novel idea is to reuse the already-generated trace-back routes to reduce the number of trace-back operations. And the spurious switching activity of the trace-back unit is reduced by making use of a clock gating method. Using the SYNOPSYS power estimation tool, DesignPower, our experimental result shows the average $40{\%}$ power reduction and $23{\%}$ area increase against the trace-back unit introduced in [1].

• Journal of electromagnetic engineering and science
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• v.11 no.4
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• pp.239-249
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• 2011

In this paper, we propose a reliable $8{\times}8$ up-down switching polar relay code based on 3GPP LTE standard, motivated by 3GPP LTE down link, which is 30 bps/Hz for $8{\times}8$ MIMO antennas, and by Arikan's channel polarization for the frequency selective fading (FSF) channels with the generator matrix $Q_8$. In this scheme, a polar encoder and OFDM modulator are implemented sequentially at both the source node and relay nodes, the time reversion and complex conjugation operations are separately implemented at each relay node, and the successive interference cancellation (SIC) decoder, together with the cyclic prefix (CP) removal, is performed at the destination node. Use of the scheme shows that decoding at the relay without any delay is not required, which results in a lower complexity. The numerical result shows that the system coded by polar codes has better performance than currently used designs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.249-250
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• 2008

In this paper, we propose the single polycrystalline silicon flash EEPROM IC with a new structure which does not need the high voltage switching circuit. The design of high voltage switching circuits which are needed for the data program and erase, has been an obstacle to develop the single-poly EEPROM. Therefore, we has proposed the new cell structure which uses the low voltage switching circuits and has designed the full chip. A new single-poly EEPROM cell is designed and the full chip including the control block, the analog block, row decoder block, and the datapath block is designed. And the each block is verified by using the computer simulation. In addition, the full chip layout is performed.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.37-43
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• 1999

Two-way addressing method has been proposed for efficient VLSI implementation of Euclidean calculation circuit for pipelined Reed-Solomon decoder. This new circuit is operating with single clock while exploiting maximum parallelism, and uses register addressing instead of register shifting to minimize the switching power. Logic synthesis shows the circuit with the new scheme takes 3,000 logic gates, which is about 40% reduction from the previous 5,000 gate implementation. Computer simulation also shows the power consumption is about 3mW. The previous implementation with multiple clock consumed about 5mW.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.10
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• pp.1794-1800
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• 2008

This paper presents a method of constructing the digital logic switching functions using PLA. First of all, we propose a MIN and MAX algebra arithmetic operation based on the Post algebra. And we discuss the T-gate which is used for realization of the MIN and MAX algebra arithmetic operation. Next, we discuss the MIN array and MAX array which are basic circuit of the PLA, also we discuss the literal property. For the purpose of the design for the digital logic switching functions using PLA, we Propose the variable partition, modular structure design, literal generator, decoder and invertor. The proposed method is the more compactable and extensibility.

• Journal of Broadcast Engineering
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• v.9 no.1
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• pp.17-31
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• 2004

This paper proposes an algorithm for the robust transmission of video in error Prone environment using multiple description codingby optimal split of DCT coefficients and rate-distortionoptimization framework. In MDC, a source signal is split Into several coded streams, which is called descriptions, and each description is transmitted to the decoder through different channel. Between descriptions, structured correlations are introduced at the encoder, and the decoder exploits this correlation to reconstruct the original signal even if some descriptions are missing. It has been shown that the MDC is more resilient than the singe description coding(SDC) against severe packet loss ratecondition. But the excessive redundancy in MDC, i.e., the correlation between the descriptions, degrades the RD performance under low PLR condition. To overcome this Problem of MDC, we propose a hybrid MDC method that controls the SDC/MDC switching according to channel condition. For example, the SDC is used for coding efficiency at low PLR condition and the MDC is used for the error resilience at high PLR condition. To control the SDC/MDC switching in the optimal way, RD optimization framework are used. Lagrange optimization technique minimizes the RD-based cost function, D+M, where R is the actually coded bit rate and D is the estimated distortion. The recursive optimal pet-pixel estimatetechnique is adopted to estimate accurate the decoder distortion. Experimental results show that the proposed optimal split of DCT coefficients and SD/MD switching algorithm is more effective than the conventional MU algorithms in low PLR conditions as well as In high PLR condition.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.18 no.1
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• pp.15-29
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• 2024

A fetoscope is an optical endoscope, which is often applied in fetoscopic laser photocoagulation to treat twin-to-twin transfusion syndrome. In an operation, the clinician needs to observe the abnormal placental vessels through the endoscope, so as to guide the operation. However, low-quality imaging and narrow field of view of the fetoscope increase the difficulty of the operation. Introducing an accurate placental vessel segmentation of fetoscopic images can assist the fetoscopic laser photocoagulation and help identify the abnormal vessels. This study proposes a method to solve the above problems. A novel encoder-decoder network with a dual-path structure is proposed to segment the placental vessels in fetoscopic images. In particular, we introduce a channel attention mechanism and a continuous convolution structure to obtain multi-scale features with their weights. Moreover, a switching connection is inserted between the corresponding blocks of the two paths to strengthen their relationship. According to the results of a set of blood vessel segmentation experiments conducted on a public fetoscopic image dataset, our method has achieved higher scores than the current mainstream segmentation methods, raising the dice similarity coefficient, intersection over union, and pixel accuracy by 5.80%, 8.39% and 0.62%, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.27-38
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• 2016

This work proposes a 12b 30MS/s 0.18um CMOS SAR ADC based on low-power composite switching with an active die area of $0.16mm^2$. The proposed composite switching employs the conventional $V_{CM}$-based switching and monotonic switching sequences while minimizing the switching power consumption of a DAC and the dynamic offset to constrain a linearity of the SAR ADC. Two equally-divided capacitors topology and the reference scaling are employed to implement the $V_{CM}$-based switching effectively and match an input signal range with a reference voltage range in the proposed C-R hybrid DAC. The techniques also simplify the overall circuits and reduce the total number of unit capacitors up to 64 in the fully differential version of the prototype 12b ADC. Meanwhile, the SAR logic block of the proposed SAR ADC employs a simple latch-type register rather than a D flip-flop-based register not only to improve the speed and stability of the SAR operation but also to reduce the area and power consumption by driving reference switches in the DAC directly without any decoder. The measured DNL and INL of the prototype ADC in a 0.18um CMOS are within 0.85LSB and 2.53LSB, respectively. The ADC shows a maximum SNDR of a 59.33dB and a maximum SFDR of 69.83dB at 30MS/s. The ADC consumes 2.25mW at a 1.8V supply voltage.