• Journal of Korea Society of Digital Industry and Information Management
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• v.10 no.1
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• pp.99-104
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• 2014

Nowadays, various researches fulfill in many communication engineering area for B4G (Beyond Forth Generation). Next LTE-A (Long Term Evolution Advanced), MU-MIMO (Multi-User Multi Input Multi Output) method raises to upgrade throughput performance. However, the method of user selection is not decided because of many types and discussions in MU-MIMO system. Many existing methods are powerful for enhancing performance but have various restrictions in practical implementation. Fairness problem is primary restriction in this area. Existing papers emphasis algorithm to increase sum-rate but we introduce an algorithm about dealing with fairness problem for real commercialization implementation. Therefore, this paper introduces new user selection method in MU-MIMO system. This method overcomes a fairness problem in SUS (Semiorthogonal User Selection) algorithm. We can use the method to get a similar sum-rate with SUS and a high fairness performance. And this paper uses a hybrid method with SC-SUS (Superposition Coding SUS) algorithm and SUS algorithm. We find a threshold value of optimal performance by experimental method. We show this performance by computer simulation with MATLAB and analysis that results. And we compare the results with another paper's that different way to solve fairness problem.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.31-40
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• 2010

This paper describes a LDPC decoder for IEEE 802.11n wireless LAN standard. The designed processor supports parity check matrix for block length of 1,944 and code rate of 1/2 in IEEE 802.11n standard. To reduce hardware complexity, the min-sum algorithm and layered decoding architecture are adopted. A novel memory reduction technique suitable for min-sum algorithm was devised, and our design reduces memory size to 25% of conventional method. The LDPC decoder processor synthesized with a $0.35-{\mu}m$ CMOS cell library has 200,400 gates and memory of 19,400 bits, and the estimated throughput is about 135 Mbps at 80 MHz@2.5v. The designed processor is verified by FPGA implementation and BER evaluation to validate the usefulness as a LDPC decoder.

• Journal of Korea Multimedia Society
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• v.14 no.10
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• pp.1275-1286
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• 2011

This paper proposes a high speed systolic array architecture for full search block matching algorithm (FBMA). The pixels of the search area for a reference block are input only one time to find the matched candidate block and reused to compute the sum of absolute difference (SAD) for the adjacent candidate blocks. Each row of designed 2-dimensional systolic array compares the reference block with the adjacent blocks of the same row in search area. The lower rows of the designed array get the pixels from the upper row and compute the SAD with reusing the overlapped pixels of the candidate blocks within same column of the search area. This designed array has no data broadcasting and global paths. The comparison with existing architectures shows that this array is superior in terms of throughput through it requires a little more hardware.

• Management Science and Financial Engineering
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• v.16 no.1
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• pp.59-79
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• 2010

This paper considers bandwidth allocation and scheduling problems on Ethernet Passive Optical Networks (EPON). EPON is one of the good candidates for the optical access network. This paper formulates the bandwidth allocation problem as a nonlinear mathematical one and characterizes the optimal bandwidth allocation which maximizes weighted sum of throughput and fairness. Based upon the characterization, two heuristic algorithms are suggested with various numerical tests. The test results show that our algorithms can be used for efficient bandwidth allocation on the EPON. This paper also shows that the WSPT (Weighted Shortest Processing Time) rule is optimal for minimization the total delay time in transmitting the traffic of the given allocated bandwidth.

• ETRI Journal
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• v.27 no.6
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• pp.768-776
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• 2005

We compare the achievable throughput of time division multiple access (TDMA) multiple-input multiple-output (MIMO) schemes illustrated in the 3rd Generation Partnership Project (3GPP) MIMO technical report, versus the sum-rate capacity of space-time multiple access (STMA). These schemes have been proposed to improve the 3GPP high speed downlink packet access (HSDPA) channel by employing multiple antennas at both the base station and mobile stations. Our comparisons are performed in multi-user environments and are conducted using TDMA such as Qualcomm's High Data Rate and HSDPA, which is a simpler technique than STMA. Furthermore, we present the unified optimal power allocation strategy for HSDPA MIMO schemes by exploiting the similarity of multiple antenna systems and multi-user channel problems.

• ETRI Journal
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• v.18 no.3
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• pp.127-145
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• 1996

A new analytic framework based on a linear algebra approach is proposed for examining the performance of a direct sequence spread spectrum (DS/SS) slotted ALOHA wireless communication network systems with delay capture. The discrete-time Markov chain model has been introduced to account for the effect of randomized time of arrival (TOA) at the central receiver and determine the evolution of the finite population network performance in a single-hop environment. The proposed linear algebra approach applied to the given Markov problem requires only computing the eigenvector ${\prod}$ of the state transition matrix and then normalizing it to have the sum of its entries equal to 1. MATLAB computation results show that systems employing discrete TOA randomization and delay capture significantly improves throughput-delay performance and the employed analysis approach is quite easily and staightforwardly applicable to the current analysis problem.

• Proceedings of the Korea Society for Simulation Conference
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• 1999.04a
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• pp.47-52
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• 1999

In this paper we propose new approximate method for the performance analysis of closed-loop production system with unreliable machines and random processing times. The approximate method decomposes the production system consisting of K machines into a set of K subsystems, each subsystem consisting of two machines separated by a finite buffer. Then, each subsystem is analyzed by analyzing method n isolation. The population constraint of the closed-loop production system is taken into account by prescribing that the sum of average buffer level in the subsystems is equal to the number of customers in the closed-loop production system,. We establish a set of equations that characterizes unknown parameters of the servers in the subsystems. An iterative procedure is then used to determine the unknown parameters. Experimental results show that these methods provide a good estimation of the throughput.

• Journal of Korean Institute of Industrial Engineers
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• v.25 no.2
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• pp.240-253
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• 1999

In this paper we propose new approximate methods for the performance analysis of closed-loop production systems with unreliable machines and random processing times. Each approximate method decomposes the production system consisting of K machines into a set of K subsystems, each subsystem consisting of two machines separated by a finite buffer. Then, each subsystem is analyzed by three different analyzing methods in isolation. The population constraint of the closed-loop production system is taken into account by prescribing that the sum of average buffer levels in the subsystems is equal to the number of customers in the closed-loop production system. We establish a set of equations that characterize unknown parameters of the servers in the subsystems. An iterative procedure is then used to determine the unknown parameters. Experimental results show that these methods provide a good estimation of the throughput.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.18-26
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n wireless LAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. From fixed-point modeling and Matlab simulations for various bit-widths, decoding performance and optimal hardware parameters such as fixed-point bit-width are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.18-${\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1355-1362
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. Our LDPC decoder adopts a block-serial architecture based on min-sum algorithm and layered decoding scheme. A novel way to store check-node values and parity check matrix reduces the sizes of check-node memory and H-ROM. An efficient scheme for check-node memory addressing is used to achieve stall-free read/write operations. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.