Journal of Korea Multimedia Society (한국멀티미디어학회논문지)

Korea Multimedia Society (한국멀티미디어학회)
권호 표지
DOI QR코드

DOI QR Code

A Systolic Array for High-Speed Computing of Full Search Block Matching Algorithm

  • Jung, Soon-Ho (Pukyong National University, Department of Computer Engineering) ;
  • Woo, Chong-Ho (Pukyong National University, Department of Computer Engineering)
  • Received : 2011.07.27
  • Accepted : 2011.09.21
  • Published : 2011.10.31
Download PDF
⟨ Previous Next ⟩

Abstract

This paper proposes a high speed systolic array architecture for full search block matching algorithm (FBMA). The pixels of the search area for a reference block are input only one time to find the matched candidate block and reused to compute the sum of absolute difference (SAD) for the adjacent candidate blocks. Each row of designed 2-dimensional systolic array compares the reference block with the adjacent blocks of the same row in search area. The lower rows of the designed array get the pixels from the upper row and compute the SAD with reusing the overlapped pixels of the candidate blocks within same column of the search area. This designed array has no data broadcasting and global paths. The comparison with existing architectures shows that this array is superior in terms of throughput through it requires a little more hardware.

Keywords

References

  1. J. L. Mitchell, W. B. Pennebaker, C. E. Fogg, and D. J. Legall, MPEG video compression standard, Chapman and Hall, 1996.
  2. S. Zhu and K. K. Ma, "A New Diamond Search Algorithm for Fast Block-Matching Mostion Estimation," IEEE Trans. on Image Processing, Vol.9, No.2, pp. 287-290, 2000. https://doi.org/10.1109/83.821744
  3. S. Y. Kung, VLSI array processors, Prentice Hall, Englewood Cliffs, NJ, 1988.
  4. Y. Huang, C. Chen, C. Tsai, C. Shen, and L. Chen, "Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results," Journal of VLSI Signal Processing 42, pp. 297-320, 2006. https://doi.org/10.1007/s11265-006-4190-4
  5. T. Komarek and P. Pirsch, "Array Architecture for Block Matching Algorithms," IEEE Trans. on Circuits and Systems, Vol.36, No.10, pp. 1301-1308, 1989. https://doi.org/10.1109/31.44346
  6. C. H. Hsieh and T. P. Lin, "VLSI Architecture for Block-Matching Motion Estimation Algorithm," IEEE Trans. on Circuits and Systems for Video Technology, Vol.2, No.2, pp. 169-175, 1992. https://doi.org/10.1109/76.143416
  7. S. B. Pan, S. S. Chae, and R. H. Park, "VLSI Architectures for Block Matching Algorithm," IEEE Trans. Circuits and Systems for Video Technology, Vol.6, pp. 67-73, 1995.
  8. H. G. Yea and Y. H. Hu, "A Novel Modular Systolic Array Architecture for Full-Search Block Matching Motion Estimation," IEEE Trans. on Circuits and Systems for Video Technology, Vol.5, No.5, pp. 407-416, 1995. https://doi.org/10.1109/76.473553
  9. C. Y. Lee and M. C. Lu "An Efficient VLSI Architecture for Full-Search Block Matching Algorithms," Journal of VLSI Signal Processing, Vol.15, pp. 275-282, 1997. https://doi.org/10.1023/A:1007915312120
  10. Y. K Lai and L. G. Chen, "A Data-Interlacing Architecture with Two-Dimensional Data- Reuse for Full-Search Block Matching Algorithm," IEEE Trans. Circuits and Systems for Video Technology, Vol.8, pp. 124-127, 1998. https://doi.org/10.1109/76.664095
  11. Y. K. Lai, Y. L. Lai, Y. C. Liu, P. C. Wu, and L. G. Chen, "VLSI Implementation of the Motion Estimator with Two-Dimensional Data- Reuse," IEEE Trans. on Consumer Electronics, Vol.44, No.3, pp. 623-628, 1998. https://doi.org/10.1109/30.713173
  12. S. Kittitornkun and Y. H. Hu, "Frame-Level Pipelined Motion Estimation Array Processor," IEEE Trans. Circuits and Systems for Video Technology, Vol.11, No.2, pp. 248-251, 2001. https://doi.org/10.1109/76.905990
  13. S. Pandian, Hegde, J. Bala, and B. George, "A Study on Block Matching Algorithms for Motion Estimation," International Journal on Computer Science and Engineering, Vol.3, No.1, pp. 34-44, 2011.
  14. M. Azadfar, "Implementation of A Optimized Systolic Array Architecture for FSBMA using FPGA for Real-time Applications," IJCSNS International Journal of Computer Science and Network Security, Vol.8, No.3, pp. 46-51, 2008.
  15. G. Hegde, C. P. RajP, and P. R. Vaya, "Implementation of Systolic Array Architecture for Full Search Block Matching Algorithm on FPGA," European Journal of Scientific Research ISSN 1450-216X, Vol.33, No.4, pp. 606-616, 2009.