• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.1
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• pp.7-12
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• 2011

This paper proposes a differential Colpitts-VCO circuit suitable for low phase noise oscillation at the sub-1V supply voltage. Oscillation with low phase noise at the sub-1V supply voltage is facilitated by employing inductors as the current sources of the proposed circuit. One of the two feedback capacitors of the single-ended Colpitts oscillator in the proposed circuit is replaced with the MOS varactor in order to further reduce the resonator loss. Post-layout simulation results using a $0.18{\mu}m$ RF CMOS technology show that the phase noises at the 1MHz offset frequency of the proposed circuit oscillating at the sub-1V supply voltages of 0.6 to 0.9 V are at least 7 dBc/Hz lower than those of the well-known cross-coupled differential VCO.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.7
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• pp.761-766
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• 2014

This study performs the analytical investigation of the oscillation voltages at the tanks of the series tuned varactor incorporating balanced common-drain, and common-gate Colpitts VCO which are able to work even at the sub-1V power supply voltages. The results the investigation predicts is verified by the simulation on the circuit behaviors of the two VCOs. The analytical investigation finds that the series tuned varactor incorporating balanced common-gate VCO generates greater oscillation voltage at the tank than the series tuned varactor incorporating balanced common-drain VCO does, which in turn is more suitable for generating the low phase noise oscillation signal from the sub-1V supply voltage than the series tuned varactor incorporating balanced common-drain VCO.

• Journal of IKEEE
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• v.18 no.4
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• pp.625-629
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• 2014

This study derives the asymptotic phase noise formula of the oscillators perturbed by the colored noises. Based on the derived formula, this study presents a sub-1V series-tuned differential Colpitts VCO. The ADS simulation result on the phase noise shows that the presented VCO exhibits about 3dBc/Hz lower phase noise at the 1MHz offset frequency from the oscillation frequency of 4.8GHz than the existing series-tuned differential Colpitts VCO with the inductor current sources.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.4
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• pp.715-720
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• 2012

This study presents a hybrid balanced voltage controlled oscillator (VCO) circuit which is suitable for low phase noise operation at sub-1V supply voltages. Half circuits of the proposed VCO use the varactor-integrated feedback capacitors in their respective circuit. The varactor-integrated feedback capacitors further increase the negative resistance of the equivalent tank thereby ensuring stable start-up of oscillation even at the sub-1V supply voltage. In addition, this work theoretically analyses the phenomenon of the increase of the negative resistance. Simulation results using a $0.18{\mu}m$ RF CMOS technology exhibit the phase noises of -122.4 to -125.5.8 dBc/Hz at 1 MHz offset from oscillation frequency of 4.87 GHz over the supply voltages of 0.6 through 0.9 V.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.2
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• pp.139-145
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• 2024

This paper presents the design of a voltage controlled oscillator (VCO) which is one of the key building blocks in modern wireless communication systems with small VCO gain (K_vco) variation. To compensate conventional large K_vco variation, a series varactor bank has been added to the conventional LC-tank with parallel capacitor bank array. And also, in order to achieve excellent phase noise performance while maintaining wide tuning range, a mixed coarse/fine tuning scheme(series varactor array and parallel capacitor array) is chosen. The switched varactor array bank is controlled by the same digital code for switched capacitor array without additional digital circuits. For use at a low voltage of 1.2V, the proposed current reference circuit in this paper used a current reference circuit for safety with the common gate removed more safely. Implemented in a TSMC 0.13㎛ CMOS RF technology, the proposed VCO can be tuned from 4.4GH to 5.3GHz with the K_vco (VCO gain ) variation of less than 9.6%. While consuming 3.1mA from a 1.2V supply, the VCO has -120dBc/Hz phase noise at 1MHz offset from the carrier of the 5.3 GHz.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.7 s.361
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• pp.7-11
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• 2007

This paper presents a multiband octa-phase LC VCO for SDR receiver. Four identical LC VCOs are connected by using series coupling transistor to obtain the octa-phase signal and low phase noise characteristic. For a multiband application, a band tuning circuit that consists of a switch capacitor circuit and two MOS varactors is proposed. As the MOS switch is on/off state, the frequency range will be varied. In addition, two varactors make the VCO be immune to process variation of the oscillation frequency. The VCO is designed in 0.18-um CMOS technology, consumes 12mA current from 1.8V supply voltage and operates with a frequency band from 885MHz to 1.342GHz (41% tuning range). As driving sub-harmonic mixer, the proposed VCO covers 3 standards(CDMA 2000 1x, WCDMA, WiBro). The measured phase noise is -105dBc@100kHz, -115dBc@1MHz, -130dBc@10MHz for CDMA 2000 1x, WCDMA, WiBro respectively.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.969-972
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• 2000

This paper proposes 1.5V-3GHz CMOS PLL with a new delay cell for operating in high frequency and multi chained two stage VCO to improve phase noise performance. The proposed multi-chained architecture is able to reduce a timing jitter or a transition spacing and the newly VCO is operating in high frequency. The PFD circuit designed to prevent fluctuation of charge pump circuit under the locking condition. Simulation results show that the tuning range of proposed VCO is wide at 1.8GHz-3.2Ghz and power dissipation is 0.6mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.117-124
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• 2009

This paper describes a 3 to 5 GHz frequency synthesizer for MB-OFDM (Multi-Band OFDM) UWB (Ultra- Wideband) application using 0.13 ${\mu}m$ CMOS process. The frequency synthesizer operates in the band group 1 whose center frequencies are 3432 MHz 3960 MHz, and 4488 MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and LO Mixer architecture are also presented in this paper. A new mixed coarse tuning scheme that utilizes the MIM capacitance, the varactor arrays, and the DAC is proposed to expand the VCO tuning range. The frequency synthesizer can also provide the clock for the ADC in baseband modem. So, the PLL for the ADC in the baseband modem can be removed with this frequency synthesizer. The single PLL and two SSB-mixers consume 60 mW from a 1.2 sV supply. The VCO tuning range is 1.2 GHz. The simulated phase noise of the VCO is -112 dBc/Hz at 1 MHz offset. The die area is 2 ${\times}$ 2mm$^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.281-286
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• 2007

In this paper, sub-circuits for 24 GHz phase locked 100ps(PLLs) using $0.5{\mu}m$ SiGe HBT are presented. They are 24 Ghz voltage controlled oscillator(VCO), 24 GHz to 12 GHz regenerative frequency divider(RFD) and 12 GHz to 1.5 GHz static frequency divider. $0.5{\mu}m$ SiGe HBT technology, which offers transistors with 90 GHz fMAX and 3 aluminum metal layers, is employed. The 24 GHz VCO employed series feedback topology for high frequency operation and showed -1.8 to -3.8 dBm output power within tuning range from 23.2 GHz to 26 GHz. The 24 GHz to 12 GHz RFD, based on Gilbert cell mixer, showed 1.2 GHz bandwidth around 24 GHz under 2 dBm input and consumes 44 mA from 3 V power supply including I/O buffers for measurement. ECL based static divider operated up to 12.5 GHz while generating divide by 8 output frequency. The static divider drains 22 mA from 3 V power supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.72-78
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• 2009

This paper proposes a low phase noise ring voltage controlled oscillator(VCO) with a standard $0.13{\mu}m$ CMOS process for PLL circuit using the VCO-gain-controlled Delay cell. The proposed Delay cell architecture with a active resistor using a MOS transistor. This method can reduced a VCO gain so that improve phase noise. And, Delay cell consist of Wide-Swing Cascode current mirror, Positive Latch and Symmetric load for low phase noise. The measurement results demonstrate that the phase noise is -119dBc/Hz at 1MHz offset from 1.9GHz. The VCO gain and power dissipation are 440MHz/V and 9mW, respectively.