Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of 1.5V-3GHz CMOS multi-chained two stage VCO

  • Yu, Hwa-Yeal (Dept. of Electronic Engineering, Inha University) ;
  • Oh, Se-Hoon (Dept. of Electronic Engineering, Inha University) ;
  • Han, Yun-Chol (Dept. of Electronic Engineering, Inha University) ;
  • Yoon, Kwang-Sub (Dept. of Electronic Engineering, Inha University)
  • Published : 2000.07.01
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Abstract

This paper proposes 1.5V-3GHz CMOS PLL with a new delay cell for operating in high frequency and multi chained two stage VCO to improve phase noise performance. The proposed multi-chained architecture is able to reduce a timing jitter or a transition spacing and the newly VCO is operating in high frequency. The PFD circuit designed to prevent fluctuation of charge pump circuit under the locking condition. Simulation results show that the tuning range of proposed VCO is wide at 1.8GHz-3.2Ghz and power dissipation is 0.6mW.

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