• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1392-1395
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• 2004

In order to successfully develop attitude and orbit control subsystem(AOCS), AOCS engineer performs hardware selection, controller design and analysis, control logic and interface verification on electrical test bed, integrated system test, polarity test, and finally verification on orbit after launching. Attitude and orbit control subsystem for KOMPSAT-2 consists of standby mode, sun mode, maneuver mode, science mode, and power safe mode to stabilize and to control the spacecraft for performing the mission. The sun mode is usually divided into sun point submode, earth search submode and safe hold submode. The maneuver mode is divided into attitude hold submode and ${\triangle}$ V submode, while the science mode divided into science coarse submode and science fine submode. Moreover, it is added to back-up mode which uses wheels as an actuator for sun mode and maneuver mode. In this paper, we describe the controller design process and the performance of the design results with respect to the sun mode and the maneuver mode based on thrusters as an actuator using on flexible model.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.36-47
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• 1998

Low power circuit techniques have been developed to realize the highest possible performance of embedded SRAM at 1V power supply with$0.5\mu\textrm{m}$ single threshold CMOS technology in which the unbalance between NMOS and PMOS threshold voltages is utilized to optimize the low power CMOS IC design. To achieve the best trade-off between the transistor drivability and the subthreshold current increase, the ground potential of memory array is raised to suppressthe subthreshold current. The problems of lower cellstability and bit-line dealy increase due to the enhanced array ground potential are evaluated to be controlled within the allowable range by careful circuit design. 160MHz, 128kb embedded SRAM with 3.4ns access time is demonstrated with the power consumption of 14.8mW in active $21.4{mu}W$ in standby mode at 1V power supply.

• Proceedings of the Korea Database Society Conference
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• 2010.06a
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• pp.33-41
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• 2010

Recently the number of IT equipment have increased. It consumes large amounts of energy and is emissions of greenhouse gases. Co2 emissions with the PC and the monitor has the highest percentage to 39% more than other IT equipment. In addition, Plan for your PC's power management and technology development is being pursued in developed countries. To reduce energy costs of organizations with large numbers of the PC and to cut down on Co2 emissions, the energy load control technology of ACPI standards-based PC IS suggested. AMI-based PC power-management system was constructed, Approximately 20% of operating a result of the test power consumption was reduced. Looking at the case of the United States, PC monitors from the University of Wisconsin-Oshkosh was Sleep mode. As a result, the monitor on a, $ 20 for a year reduced energy costs. In GE(General Electronic), Approximately 75,000 PC's power setting time was Monitor Off :15 minutes/ Hard Drives Off 30 minutes/ System Standby 30 minutes/ Hibernation mode 2 hours. 1 year, electric bill was $ 2.5 million savings and 3 years electric bill was $ 6.5 million savings. Measuring energy usage data, using the measured data, electric energy management technology is not. Platform development to measure energy usage for Individual energy-consuming equipment is urgently required.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3A
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• pp.221-229
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• 2007

In this paper, we propose and analyze the optimized sleep mode for a mobile node (MN) in IEEE 802.16e wireless metropolitan area networks. Because a MN in a sleep mode specified in 802.16e specification should maintain state information with the base station currently attached, it must renew sleep state with a new base station after handover which leads to unnecessary waste of battery power. Noting that the mobility pattern of a MN is independent of call arrival patterns, we propose an optimized sleep mode to eliminate unnecessary standby period of a MN in sleep state after handover. We also propose an analytical model for the proposed scheme in terms of power consumption and the initial call response time. Simulation studies that compare the performance between the sleep mode and the optimized sleep mode show that our scheme marginally increases initial call response delay with the huge reduction in power consumption.

• Journal of IKEEE
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• v.16 no.3
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• pp.265-273
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• 2012

Data stability and leakage power dissipation have become a critical issue in scaled SRAM design. In this paper, an advanced 8T SRAM cell improving the read and write stability of data storage elements as well as reducing the leakage current in the idle mode is presented. During the read operation, the bit-cell keeps the noise-vulnerable data 'low' node voltage close to the ground level, and thus producing near-ideal voltage transfer characteristics essential for robust read functionality. In the write operation, a negative bias on the cell facilitates to change the contents of the bit. Unlike the conventional 6T cell, there is no conflicting read and write requirement on sizing the transistors. In the standby mode, the built-in stacked device in the 8T cell reduces the leakage current significantly. The 8T SRAM cell implemented in a 130 nm CMOS technology demonstrates almost 100 % higher read stability while bearing 20 % better write-ability at 1.2 V typical condition, and a reduction by 45 % in leakage power consumption compared to the standard 6T cell. The stability enhancement and leakage power reduction provided with the proposed bit-cell are confirmed under process, voltage and temperature variations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2015.07a
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• pp.98-101
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• 2015

최근, 텔레비전을 시청하지 않는 대기 상태에서의 셋톱박스의 대기 전력이 여타 가전기기의 대기 전력보다 10 배 이상을 상회하고 있어, 셋톱박스의 대기전력 저감은 국가적으로도 관심을 받고 있다. 셋톱박스의 대기전력 저감을 위해 대기상태의 셋톱박스의 최소전력 동작 모드인 수동대기모드가 제안되었지만, 셋톱박스가 수동대기모드에서는 셋톱박스의 업데이트 및 제어가 어려우므로, 셋톱박스의 수동대기모드 활용은 어려울 것이다. 본 논문은 수동대기모드에 가까운 대기전력을 소모하면서도 대기상태에서도 셋톱박스의 업데이트를 제공할 수 있는 망연동수동대기 모드를 정의하고, 망연동수동대기모드를 이용한 셋톱박스의 업데이트를 위한 셋톱박스 제어기법을 제안하고, 이 제어 기법을 위한 셋톱박스와 네트워크의 구조, 기능, 시그널링에 대해 설명한다. 본 논문의 망연동수동대기모드와 제어 방안은 셋톱박스 사업자 측면에서 활용성이 높으므로, 낮은 대기전력을 소모하는 셋톱박스 시장을 활성화하여 국가 및 세계적인 전력 감소에 큰 기여를 할 것이다.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1348-1357
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• 2015

Under traditional unified power quality conditioner (UPQC) control, a UPQC series converter (SC) is mainly used to handle grid-side power quality problems while its parallel converter (PC) is mainly used to handle load-side power quality problems. The SC and PC are relatively independent. The SC is usually in standby mode and it only runs when the grid voltage abruptly changes. In this paper, novel UPQC coordinated control strategies are proposed which use the SC to share the reactive power compensation function of the PC especially without grid-side power quality problems. However, in some cases, there will be a circulating current between the SC and the PC, which will probably influence the compensation fashion, the compensation capacity, or the normal work of the UPQC. Through an active power circulation analysis, strategies with and without a circulating current are presented which fuses the reactive power allocation strategy of the SC and the PC, the composite control strategy of the SC and the compensation strategy of the DC storage unit. Both of the strategies effectively solve the SC long term idle problem, limit the influence of the circulating current, optimize all of the UPQC units and reduce the production cost. An analysis, along with simulation andexperimental results, is presented to verify the feasibility and effectiveness of the proposed control strategies.

• International Journal of Contents
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• v.18 no.1
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• pp.76-84
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• 2022

Tidal power generation plays a critical role in reducing greenhouse gas emissions. It uses a tidal force generated by gravitational force between the moon, the earth, and the sun. The change of seawater height generates the tide-generating force, and the magnitude of the change is the tide level. The tide level change has the same period as the tide-generating force twice a day, every 29.5 days, every year, and every 18.6 years. Sihwa Lake Tidal Power Station is Korea's first tidal power plant that began commercial power generation in August 2011 and has been accumulating a large volume of data on electricity production, power generation sales, sluice displacement, and tide levels. The purpose of this paper was to analyze the impact of the inefficiency factors affecting production and the tidal level change on tidal power generation and their characteristics using Sihwa Lake Tidal Power's operational performance data. Throughout this paper we show that tidal power generating operation is accurately predicting the trends of magnitude of tidal force to be periodical for each day. determining the drop to initiate the water turbine generator factoring the constraints on the operation of Sihwa Lake, and reflecting the water discharge through the floodgate and water turbine during the standby mode in the power generation plan to be in the optimal condition until the initiation of the next power generation can maximize power generation.

• Journal of IKEEE
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• v.18 no.4
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• pp.586-592
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• 2014

In this paper, high efficiency power management IC(PMIC) with DT-CMOS(Dynamic threshold voltage Complementary MOSFET) switching device is presented. PMIC is controlled PWM control method in order to have high power efficiency at high current level. The DT-CMOS switch with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuit consist of a saw-tooth generator, a band-gap reference(BGR) circuit, an error amplifier, comparator circuit, compensation circuit, and control block. The saw-tooth generator is made to have 1.2MHz oscillation frequency and full range of output swing from supply voltage(3.3V) to ground. The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on current mode PWM control circuits and low on-resistance switching device, achieved the high efficiency nearly 96% at 100mA output current. And Buck converter is designed along LDO in standby mode which fewer than 1mA for high efficiency. Also, this paper proposes two protection circuit in order to ensure the reliability.