• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.196-198
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• 2007

본 논문에서는 가전 및 사무용 전원장치가 대기모드 상태에 있는 경우의 전력소모를 줄일 수 있는 PWM(Pulse Width Modulation) IC를 설계하였다. 설계된 PWM IC는 전원장치가 정상상태에서 동작하는 경우 전원장치 출력단에서 피드백 받은 신호의 크기에 따라 40 ~ 60kHz의 구동 주파수를 가지는 스위칭 소자 구동 신호를 내보내고, 대기모드 상태에서 동작하는 경우에는 최소 33KHz의 주파수를 가지는 신호를 내보내도록 설계되었다. 각각의 경우에 스위칭 소자 구동 신호의 듀티비는 정상상태인 경우에는 20 ~ 88%, 대기모드 상태인 경우에는 1%이내가 되도록 설계하였다. 시뮬레이션을 통해 검증한 결과 대기모드 상태에서 전원장치의 전력소모량은 0.2W 정도로 작게 나타남을 확인하였다.

• Journal of Power Electronics
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• v.15 no.4
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• pp.1131-1138
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• 2015

This study presents an input-powered high-efficiency interface circuit for energy harvesting systems, and introduces a zero standby power design to reduce power consumption significantly while removing the external power supply. This interface circuit is composed of two stages. The first stage voltage doubler uses a positive feedback control loop to improve considerably the conversion speed and efficiency, and boost the output voltage. The second stage active diode adopts a common-grid operational amplifier (op-amp) to remove the influence of offset voltage in the traditional comparator, which eliminates leakage current and broadens bandwidth with low power consumption. The system supplies itself with the harvested energy, which enables it to enter the zero standby mode near the zero crossing points of the input current. Thereafter, high system efficiency and stability are achieved, which saves power consumption. The validity and feasibility of this design is verified by the simulation results based on the 65 nm CMOS process. The minimum input voltage is down to 0.3 V, the maximum voltage efficiency is 99.6% with a DC output current of 75.6 μA, the maximum power efficiency is 98.2% with a DC output current of 40.4 μA, and the maximum output power is 60.48 μW. The power loss of the entire interface circuit is only 18.65 μW, among which, the op-amp consumes only 2.65 μW.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.128-133
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• 2008

Phase-change random access memory (PRAM) chip cell phase of amorphous state is rapidly changed to crystal state above 160 Celsius degree within several seconds during Infrared (IR) reflow. Thus, on-board programming method is considered for PRAM chip programming. We demonstrated the functional 512Mb PRAM with 90nm technology using several novel core circuits, such as metal-2 line based global row decoding scheme, PN-diode cells based BL discharge (BLDIS) scheme, and PMOS switch based column decoding scheme. The reverse-state standby current of each PRAM cell is near 10 pA range. The total leak current of 512Mb PRAM chip in standby mode on discharging state can be more than 5 mA. Thus in the proposed BLDIS control, all bitlines (BLs) are in floating state in standby mode, then in active mode, the activated BLs are discharged to low level in the early timing of the active period by the short pulse BLDIS control timing operation. In the conventional sense amplifier, the simultaneous switching activation timing operation invokes the large coupling noise between the VSAREF node and the inner amplification nodes of the sense amplifiers. The coupling noise at VSAREF degrades the sensing voltage margin of the conventional sense amplifier. The merit of the proposed sense amplifier is almost removing the coupling noise at VSAREF from sharing with other sense amplifiers.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.745-753
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• 2016

This paper presents a fully synthesizable low power interconnect bus for millimeter-scale wireless sensor nodes. A segmented ring bus topology minimizes the required chip real estate with low input/output pad count for ultra-small form factors. By avoiding the conventional open drain-based solution, the bus can be fully synthesizable. Low power is achieved by obviating a need for local oscillators in member nodes. Also, aggressive power gating allows low-power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with a power management unit that has nW standby mode. A 3-module system including the bus is fabricated in a 180 nm process. The entire system consumes 8 nW in standby mode, and the bus achieves 17.5 pJ/bit/chip.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.397-398
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• 2013

Fairchild Green Mode off line buck switch for low standby power consumption and high reliability is presented. By reducing operating current and optimizing switching frequency, 20mW power consumption is achieved. High performance trans-conductance amplifier and green mode function improve the ripple and regulation in the output voltage. The conventional $FPS^{TM}$ buck and novel Fairchild buck switch are compared to show the improvement of performance. Experimental results are showed using 2W evaluation board.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.51-55
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• 2007

Generally, PLC (Power Line Communication) based home automation devices such as wall switch, walt socket, gas controller, etc, must maintain wake-up status at all time to control other electronic devices and monitor their on/off status whether they are in service or not. In order to reduce the unnecessary energy consumption during the standby mode, the new power-saving PLC 2 ports wall switch has been developed, separating PLC communication part and controller part and introducing sleep mode. In addition, to expand life cycle of PLC product and to reduce the rate of product failure in active mode, the instant controlling method in controlling process is adopted instead of the maintenance controlling method. In comparison to the earlier model, the new 2 ports PLC wall switch has reduced power by 0.95[W] less in standby mode and 3.2[W] less in active mode than the previous one.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.2
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• pp.57-64
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• 2007

This paper proposed the low power texture cache for mobile 3D graphics accelerators. It is very important to reduce the leakage power in the standby mode for mobile 3D graphics accelerators and the memory access latency of texture mapping in the active mode which needs a large memory bandwidth. The proposed structure reduces the leakage power using variable threshold values of power mode transitions according to the selected texture filtering algorithms of application programs, which has the run time gain for texture mapping. In the trace driven cache simulation the proposed structure shows the best 7% performance gain to the previous MSA cache according to the new performance metric considering both normalized leakage power and run time impact.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.59-66
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• 2015

In this paper, we propose a method of improving the light-load efficiency of DC-DC buck converter using 4bit SAR-ADC (Successive Approximation ADC) for a LDO or a power transistor size selection technique. The proposed circuit selects power transistor sizes depending on load current so that improves the light-load efficiency of the DC-DC buck converter. For this, we select the power transistor size with a cross point of the switching loss and the conduction loss. Also, when the IC operates in standby mode or sleep mode, a LDO mode is selected for improving the efficiency. The proposed circuit selects power transistor sizes(X1, X2, X4, X8) with 4 bits and its efficiency is higher about the maximum of 25% at the light-load than that of a single transistor size. Input voltage and output voltage are 5V and 3.3V for maximum load currents of 500mA.

• Proceedings of the Korean Society of Computer Information Conference
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• 2011.01a
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• pp.281-282
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• 2011

본 논문에서는 휴대기기의 설계에서 전원절약기법에 대하여 연구하였다. 기존의 휴대형기기는 기능이 단순하고, 저 성능이였으나 점차 휴대형기기의 성능향상으로 고소비전력화 되고 있다. 본 논문에서는 주처리기와 대기모드 처리기를 사용하는 방안을 제안하고, 비교 검토하였다.

• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.514-515
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• 2010

본 논문은 다중출력 스위칭 모드 전원 공급장치의 경부하 상태에서 2차측의 부하 전압안정을 위하여 일반적으로 사용하는 선형 전압조정기의 제어기 내 부하전류정보를 이용하여, 대기모드를 구현함으로써 시스템의 효율을 향상 시켰다. 제안된 회로의 동작원리를 설명하고 이를 시뮬레이션을 통하여 확인하고 20W급 하드웨어 프로토타입을 이용하여 검증하였다.