• Journal of IKEEE
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• v.28 no.2
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• pp.234-238
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• 2024

This paper presents a study on the integration of 3D-stacked dual-tip RRAM with a CNN accelerator architecture, leveraging its low drive current characteristics and scalability in a 3D stacked configuration. The dual-tip structure is utilized in a parallel connection format in a synaptic array to implement multi-level capabilities. It is configured within a Network-on-chip style accelerator along with various hardware blocks such as DAC, ADC, buffers, registers, and shift & add circuits, and simulations were performed for the CNN accelerator. The quantization of synaptic weights and activation functions was assumed to be 16-bit. Simulation results of CNN operations through a parallel pipeline for this accelerator architecture achieved an operational efficiency of approximately 370 GOPs/W, with accuracy degradation due to quantization kept within 3%.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.12
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• pp.986-991
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• 2018

In this paper, an A/D conversion module was designed and fabricated to improve the dynamic range of wideband digital receivers. The A/D conversion module for expanding the dynamic range converts signals into a digital signal by branching the input signal into the normal path and the amplification path according to the input signal level. Test results of the fabricated module show that the normal path of the A/D conversion module converts an input level of -57 dBm to -12 dBm into a digital signal, and the amplification path converts an input level of -30 dBm to +12 dBm into a digital signal without distortion. This translates to an input dynamic range characteristic of 69 dB. Moreover, it is confirmed that the constant output characteristic is exhibited at an instantaneous bandwidth of 100 MHz.