• Journal of the Korean institute of surface engineering
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• v.41 no.2
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• pp.48-50
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• 2008

Solid phase crystallization (SPC) of amorphous silicon is usually conducted at around $600^{\circ}C$ since it is used in the application of flat panel display using thermally susceptible glass substrate. In this study we conducted SPC experiments at temperatures higher than $600^{\circ}C$ using silicon wafers. Crystallization rate becomes dramatically rapid at higher temperatures since SPC kinetics is controlled by nucleation with high value of activation energy. We report SPC kinetics of high temperatures compared to that of low temperatures.

• Journal of the Korean institute of surface engineering
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• v.43 no.1
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• pp.7-11
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• 2010

Solid phase crystallization (SPC) is a simple method in producing a polycrystalline phase by annealing amorphous silicon (a-Si) in a furnace environment. Main motivation of the crystallization technique is to fabricate low temperature polycrystalline silicon thin film transistors (LTPS-TFTs) on a thermally susceptible glass substrate. Studies on SPC have been naturally focused to the low temperature regime. Recently, fabrication of polycrystalline silicon (poly-Si) TFT circuits from a high temperature polycrystalline silicon process on steel foil substrates was reported. Solid phase crystallization of a-Si films proceeds by nucleation and growth. After nucleation polycrystalline phase is propagated via twin mediated growth mechanism. Elliptically shaped grains, therefore, contain intra-granular defects such as micro-twins. Both the intra-granular and the inter-granular defects reflect the crystallinity of SPC poly-Si. Crystallinity and SPC kinetics of high temperatures were compared to those of low temperatures using Raman analysis newly proposed in this study.

• Journal of Korean Vacuum Science & Technology
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• v.2 no.2
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• pp.97-100
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• 1998

We have investigated the effects of crystalline activation on solid phase crystallization (SPC) of amorphous silicon (a-Si) thin films. Wet blasting and self ion implantation were employed as the activation treatments to induce macro or micro crystalline damages on deposited a-Si films. Low temperature and larger grain crystallization were obtained by the applied two-step activation. High degree of crystallinity was also observed on both furnace and rapid SPC. crystalline activations showed the promotion of nucleation on the activated regions and the retardation of growth in an amorphous matrix in SPC. The observed behavior of two-step SPC was strongly dependent on the applied activation and annealing processes. It was also found that the diversified effects by macro and micro activations on the SPC were virtually diminished as the annealing temperature increased.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.129-130
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• 2008

Polycrystalline silicon (poly-Si) Schottky barrier thin film transistors (SB-TFT) are fabricated by erbium silicided source/drain for n-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method. The fabricated poly-Si SB-TFTs have a large on/off current ratio with a low leakage current. Moreover, the electrical characteristics of poly-Si SB TFTs are significantly improved by the additional forming gas annealing in 2 % $H_2/N_2$, because the interface trap states at the poly-Si grain boundaries and at the gate oxide/poly-Si channel decreased.

• Journal of the Korean Vacuum Society
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• v.14 no.1
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• pp.24-28
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• 2005

A typical method for obtaining poly-Si films is the solid phase crystallization(SPC) of amorphous Si. Advantages of SPC are uniformity, process quality and low cost of production. However, high process temperature and long process time prevent the employment of SPC process on thermally susceptible glass substrate. In this parer, we propose a new method that applies an alternating magnetic field during crystallization annealing in an alternating magnetic field crystallization(AMFC) system for lowering process temperature and shorter process time of SPC. When we crystallized, in the case of SPC, annealing time is 24 hours at 570℃. But in the case of AMFC, annealing time is only 20 minutes at the same temperature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.11a
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• pp.89-93
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• 1995

Effects of hydrogenation in amorphous silicon rile growths on Solid Phase Crystallization (SPC) was investigated using x-ray diffractometry, energy dispersive Spectroscopy, and Raman spectrum. Interdiffusion of barium(Ba) and aluminum(Al) compounds of corning substrate was observed in both of rf sputtering and LFCVD films under the low temperature(580$^{\circ}C$) annealing. Low degree of crystallinity resulted from the interdiffusion was obtained. Highly applicable degree of crystallinity was obtained through the mechanical damage induced surface activation on amorphous silicon films. X-ray diffraction intensity of (111) orientation was used to characterize the degree of crystallinity of SPC. Nucleation and growth rate in SPC could be controllable through the employed surface treatment. IIydrogenated LPCVD films showed the superior crystallinity to non-hydrogenated sputtering films. Insignificant effects of activation treatment in sputtered film was of activation treatment in sputtered film was observed on SPC.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.60-61
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• 2007

In this paper, the p-channel poly Si thin-film transistors (Poly-Si TFT's) using formed by solid phase crystallization (SPC) on glass substrate were fabricated. And we propose an ONO(Oxide-Nitride-Oxide) multilayer as the gate insulator for poly-Si TFT's to indicate non-volatile memory (NVM) effect. Poly-Si TFT is investigated by measuring the electrical properties of poly-Si films, such as I-V characteristics, on/off current ratio. NVM characteristics is showed by measuring the threshold voltage change of TFT through I-V characteristics.

• Electrical & Electronic Materials
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• v.10 no.8
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• pp.794-799
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• 1997

Poly-Si films have been prepared by solid phase crystallization of LPCVD(low-pressure CVD) amorphous silicon. The crystallinity of poly-Si films has been derived from UV reflectance spectrum and lies in the range between 70% and 80% . From XRD measurement the peak at 28.2$^{\circ}$from (111) plane is dominantly detected in the SPC poly-Si films, The average grain size of poly-Si film is determined by the image of SEM and varies from 4000 $\AA$ to 8000$\AA$. The electrical conductivity of as-deposited amorphous silicon film is about 2.5$\times$10$^{-7}$ ($\Omega$.cm)$^{-1}$ , and 3~4$\times$10$^{-6}$ ($\Omega$.cm)$^{-1}$ of room temperature conductivity is the SPC poly-Si films. The conductivity activation energies are 0.5~0.6 eV or the 500$\AA$-thick poly-Si films.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.05a
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• pp.42-45
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• 1992

The poly silicon thin films were prepared by solid phase crystallization at 600$^{\circ}C$ of amorphous silicon films deposited on Corning 7059 glass and (100) silicon wafer with thermally grown SiO$_2$substrate by plasma enhanced chemical vapor deposition with varying rf power, deposition temperature, total flow rate. Crystallization time, microstructure, absorption coefficients were investigated by RAMAN, XRD analysis and UV transmittance measurement. Crystallization time of amorphous silicon films was increased with increasing rf power, decreasing deposition temperature and decreasing total flow rate.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.356-356
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• 2013

Monolithic 3D-IC는 현대 집적회로에서 interconnect로 인해 발생되는 여러 문제들을 해결하기 위해 새롭게 제시되고 있는 기술적 개념으로 구현 시 하위 소자 및 interconnet들에 영향을 주지 않는 저온공정이 필수적이다. 특히 germanium (Ge)은 낮은 녹는점 및 높은 캐리어 이동도 덕분에 3D-IC 구현 시 상위 소자의 channel 물질에 적합한 것으로 알려져 있다. 최근 이러한 Ge을 결정화하기 위해 solid phase crystallization (SPC), metal induced crystallization (MIC), laser annealing과 같은 결정화 방법들이 보고되고 있다. 현재까지 SPC 방법에 의해 얻어진 poly-Ge의 도핑농도 및 이동도와 같은 전기적 특성에 대한 분석은 수행된 바 있으나 3D-IC 공정에 적용이 가능한 MIC 기술을 통해 얻어진 poly Ge 필름에 대한 전기적 특성분석은 부족한 상황이다. 본 연구는 SPC 뿐만 아니라 MIC 방법을 통해 ${\alpha}$-Ge를 결정화시키고 얻어진 poly-Ge 필름의 전기적 특성을 XRD 및 hall effect measurement를 통해 분석하였다. 특히 일반적으로 Ge 내에서 p-type dopant로 동작을 하는 defect과 n-type dopant인 phosphorus 관계를 고려하여 여러 온도에서 SPC 및 MIC에 의해 얻어진 phosphorus doped poly-Ge 필름들의 전기적 특성을 분석하였다.