• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.87-94
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• 2001

A soft error rate for DRAM was predicted in connection with the leakage current in cell capacitor. The charge in cell capacitor was decreased during the DRAM operation, and soft error retes due to the leakage current were calculated in various operation mode of DRAM. It was found that the soft error rate of the /bit mode was dominant with small leakage current, but as increasing the leakage current memory mode shown the dominant effect on soft error rate. Using the 256M grade DRAM structure it was predicted that the soft error rate was influenced by the change of the cell capacitance, bit line capacitance, and the input voltage sensitivity of sense amplifier, and these results can be used to the design of the optimum cells in the next generation DRAM development.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.2
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• pp.55-61
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• 1999

A soft error rate (SER) simulator for DRAM was developed. In comparison to the other SER simulator using device simulator or Monte Carlo simulator, the proposed simulator substantially reduced the CPU time using an analytical model for the alpha-particle-induced charge collection. By analysing the soft error modes in DRAM, the bit-bar mode was identified as the main cause of soft error. Using the new SER simulator, SER of 256M DRAM was investigated and it was found that the storage capacitance had a 5fF margin.

• Journal of the Korean Operations Research and Management Science Society
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• v.31 no.3
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• pp.1-10
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• 2006

In this paper we deal with a cell planning issue arisen in a CDMA based multicast network. In a CDMA based wireless network, a terminal can significantly reduce the bit error rate via the cohesion of data streams from multiple base stations. In this case, multiple base stations have to be operated according to a common time line. The cells whose base stations are operated as such are called soft-combined cells. Therefore, a terminal can take advantage of error rate reduction, if the terminal is in a soft-combined cell and at least one neighboring cell is also soft-combined. However, as soft-combining operation gives heavy burden to the network controller, the limited number of cells can be soft-combined. Our problem us to find a limited number of soft-combined cells such that the benefit of the soft-combining operation is maximized.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.6
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• pp.507-511
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• 2006

We investigated accelerated soft error rate (ASER) in static random access memory (SRAM) cells of thin film transistor (TFT) type. The effects on ASER by cell density, buried nwell structure, operational voltage, and polysilicon-2 layer thickness were examined. The increase in the operational voltage, and the decrease in the density of SRAM cells, respectively, resulted in the decrease of ASER values. The SRAM chips with buried nwell showed lower ASER than those with normal well structure did. The ASER decreased as the test distance from alpha source to the sample increased from $7{\mu}m\;to\;15{\mu}m$. As the polysilicon-2 thickness increased up to $1000\;{\AA}$, the ASER decreased exponentially. In conclusion, the best condition for low soft error rate, which is essential to obtain highly reliable SRAM device, is to apply the buried nwell structure scheme and to fabricate thin film transistors with the thick polysilicon-2 layer

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.1
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• pp.128-136
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• 2008

In this paper, we propose a new cache structure for effective error correction of soft error. We added check bit and SEEB(soft error evaluation block) to evaluate the status of cache line. The SEEB stores result of parity check into the two-bit shit register and set the check bit to '1' when parity check fails twice in the same cache line. In this case the line where parity check fails twice is treated as a vulnerable to soft error. When the data is filled into the cache, the new replacement algorithm is suggested that it can only use the valid block determined by SEEB. This structure prohibits the vulnerable line from being used and contributes to efficient use of cache by the reuse of line where parity check fails only once can be reused. We tried to minimize the side effect of the proposed cache and the experimental results, using SPEC2000 benchmark, showed 3% degradation in hit rate, 15% timing overhead because of parity logic and 2.7% area overhead. But it can be considered as trivial for SEEB because almost tolerant design inevitably adopt this parity method even if there are some overhead. And if only parity logic is used then it can have $5%{\sim}10%$ advantage than ECC logic. By using this proposed cache, the system will be protected from the threat of soft error in cache and the hit rate can be maintained to the level without soft error in the cache.

• KIEE International Transactions on Electrophysics and Applications
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• v.5C no.6
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• pp.242-245
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• 2005

We compared and analyzed ASER (Accelerated Soft Error Rate) for cell structures and metal plate capacitance in the fabricated 16M SRAM. Application of the BNW (Buried NWELL) lowered the ASER value compared to the normal well structure. By applying the metal plate capacitor with the BNW, the lowest ASER value can be obtained. The thinner oxide thickness of the metal plate capacitor provides higher capacitance and lower ASER value. The ASER is improved from 2200 FIT to 1000 FIT after sole application of the BNW. However, it is dramatically improved to 15 FIT once the metal plate capacitor is additionally applied.

• KIEE International Transactions on Electrophysics and Applications
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• v.3C no.1
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• pp.15-18
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• 2003

The characteristics of accelerated soft error rate (ASER) for fabricated 8M SRAM are evaluated for various well structures. The application of the Buried NWell (BNW) and the variations of each well structure, well dose in process conditions are checked by ASER failure in time (FIT) in terms of reliability. The application of only the BNW shows the lowest ASER FIT value. The BNW added to the Buried PWell (BPW) shows a 200% increase and the BNW plus the Striped BPW (SBPW) shows a 100% increase compared to applying the BNW. The cases of applying SBPW show very high ASER FIT.

• Journal of Information Processing Systems
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• v.7 no.3
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• pp.435-446
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• 2011

Microprocessors are becoming increasingly vulnerable to soft errors due to the current trends of semiconductor technology scaling. Traditional redundant multi-threading architectures provide perfect fault tolerance by re-executing all the computations. However, such a full re-execution technique significantly increases the verification workload on the processor resources, resulting in severe performance degradation. This paper presents a pro-active verification management approach to mitigate the verification workload to increase its performance with a minimal effect on overall reliability. An anomaly-speculation-based filter checker is proposed to guide a verification priority before the re-execution process starts. This technique is accomplished by exploiting a value similarity property, which is defined by a frequent occurrence of partially identical values. Based on the biased distribution of similarity distance measure, this paper investigates further application to exploit similar values for soft error tolerance with anomaly speculation. Extensive measurements prove that the majority of instructions produce values, which are different from the previous result value, only in a few bits. Experimental results show that the proposed scheme accelerates the processor to be 180% faster than traditional fully-fault-tolerant processor with a minimal impact on overall soft error rate.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2020.11a
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• pp.241-243
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• 2020

The high computational complexity of deep learning algorithms has led to the development of specialized hardware architectures. However, soft errors (bit flip) may occur in these hardware systems due to voltage variation and high energy particles. Many error correction methods have been proposed to counter this problem. In this work, we analyze an error correction mechanism based on repetition codes and an activation function. We test this method by injecting errors into weight filters and define an ideal error rate range in which the proposed method complements the accuracy of the model in the presence of error.

• Nuclear Engineering and Technology
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• v.40 no.1
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• pp.69-76
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• 2008

Most pressurized water reactors use Venturi flow meters to measure the feedwater flow rate. However, fouling phenomena, which allow corrosion products to accumulate and increase the differential pressure across the Venturi flow meter, can result in an overestimation of the flow rate. In this study, a soft-sensing model based on fuzzy support vector regression was developed to enable accurate on-line prediction of the feedwater flow rate. The available data was divided into two groups by fuzzy c means clustering in order to reduce the training time. The data for training the soft-sensing model was selected from each data group with the aid of a subtractive clustering scheme because informative data increases the learning effect. The proposed soft-sensing model was confirmed with the real plant data of Yonggwang Nuclear Power Plant Unit 3. The root mean square error and relative maximum error of the model were quite small. Hence, this model can be used to validate and monitor existing hardware feedwater flow meters.