KIEE International Transactions on Electrophysics and Applications

The Korean Institute of Electrical Engineers (대한전기학회)
권호 표지

Accelerated Soft Error Rate Study with Well Structures

  • Kim, Do-Woo (Memory R & D, Hynix Semiconductor Inc.,) ;
  • Gong, Myeong-Kook (Memory R & D, Hynix Semiconductor Inc.) ;
  • Wang, Jin-Suk (Dept. of Electrical and Electronic Engineering, Chungnam National University)
  • Published : 2003.01.01
Download PDF
⟨ Previous Next ⟩

Abstract

The characteristics of accelerated soft error rate (ASER) for fabricated 8M SRAM are evaluated for various well structures. The application of the Buried NWell (BNW) and the variations of each well structure, well dose in process conditions are checked by ASER failure in time (FIT) in terms of reliability. The application of only the BNW shows the lowest ASER FIT value. The BNW added to the Buried PWell (BPW) shows a 200% increase and the BNW plus the Striped BPW (SBPW) shows a 100% increase compared to applying the BNW. The cases of applying SBPW show very high ASER FIT.

Keywords

References

  1. Craig Lage et al., 'Soft Error Rate and Stored Charge Requirements in Advanced High Density SRAMs,' IEEE International Electron Devices Meeting, pp. 821-824, 1993
  2. Paul M. Carter et a1., 'Influence on Soft Error Rates in SRAMs,' IEEE J. Solid-State Circuits, vol. SC-22, no. 3, pp.430-436, 1987
  3. David Burnett et a1., 'Soft-Error-Rate Improvement in Advanced BiCMOS SRAMs,' IEEE International Reliability Physics Symposium, pp. 156-160, 1993
  4. Shuji Murakami et a1., 'Improvement of Soft-Error Rate in MOS SRAMs' IEEE J. Solid-State Circuits, vol. 24,no. 4,pp. 869-873, 1989
  5. Y. Okazaki et al., 'New Well Structure for Deep Subum CMOS/ VolBiCMOS using Thin Epitaxy over Buried Layer and Trench Isolation,' Symposium on VLSI Technology, pp. 83-84, 1990
  6. Sai-Wai Fu et a1., 'Alpha-Partic1e-Induces Charge Collection Measurements and the Effectiveness of a Novel p-Well Protection Barrier on VLSI Memories,' IEEE Transactions on Electron Devices, vol. ED-32, no. 1, pp. 49-54, 1985
  7. Barbara Chappell et a1., 'Stability and SER Analysis of SRAM Cells,' IEEE Transactions on Electron Devices, vol. ED-32, no. 2, pp. 463-470, February 1985
  8. Hiroshi Momose, 'A P-Type Buried Layer for Protection against Soft Error in High Density CMOS SRAMs,' IEEE International Electron Devices Meeting, pp. 706-709, 1984
  9. Larry D. Edmonds, 'A Simple Estimate of FunnelingAssisted Charge Collection,' IEEE Transactions on Nuclear Science, vol. 38, no. 2, pp. 828-833, April 1991