• International Journal of Contents
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• 제7권1호
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• pp.23-28
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• 2011

In a SoC (system-on-chip) design, a design complexity is a big bottleneck. In order to overcome the design complexity, platform based design method is widely adopted for designers. Most complex SoCs need a heterogeneous design development environment for hardware and software co-design. In this paper, we discuss about some kinds of verification approaches with platform based design methodology at various abstraction levels of SoC design. We separate the verification process to two steps according to the different levels of verification. We employ a flexible SoC design environment to support simultaneous hardware and software development. We demonstrate the verification strategy of a target SoC design, IEEE 802.11a WLAN SoC.

• 전자통신동향분석
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• 제35권2호
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• pp.69-78
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• 2020

Small portable devices such as mobile phones and laptops currently display a trend of high power consumption owing to their characteristics of high speed and multifunctionality. Low-power SoC design is one of the important factors that must be considered to increase portable time at limited battery capacities. Popular low power SoC design techniques include clock gating, multi-threshold voltage, power gating, and multi-voltage design. With a decreasing semiconductor process technology size, leakage power can surpass dynamic power in total power consumption; therefore, appropriate low-power SoC design techniques must be combined to reduce power consumption to meet the power specifications. This study examines several low-power SoC design trends that reduce semiconductor SoC dynamic and static power using EDA tools. Low-power SoC design technology can be a competitive advantage, especially in the IoT and AI edge environments, where power usage is typically limited.

• IT SoC Magazine
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• 통권6호
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• pp.38-42
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• 2005

• IT SoC Magazine
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• 통권14호
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• pp.22-26
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• 2006

미국 샌프란시스코에서 지난 7월 24일부터 28일까지 5일간 제43회 Design Automation Conference(DAC)가 개최되었다. 500여개의 IP/SoC 관련 기업 및 대학이 참가하여 SoC 설계분야의 이슈와 해결방안을 논의하였다.

• IEIE Transactions on Smart Processing and Computing
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• 제5권1호
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• pp.55-62
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• 2016

In this paper, we propose a hybrid multi.system-on-chip (H-MSoC) architecture that provides a high-flexibility system in a rapid development time. The H-MSoC approach provides a flexible system-on-chip (SoC) architecture that is easy to configure for physical- and application-layer development. The physical- and application-layer aspects are dynamically designed and modified; hence, it is important to consider a design methodology that supports rapid SoC development. Physical layer development refers to intellectual property cores or other modular hardware (HW) development, while application layer development refers to user interface or application software (SW) development. H-MSoC is built from multi-SoC architectures in which each SoC is localized and specified based on its development focus, either physical or application (hybrid). Physical HW development SoC is referred to as physical-SoC (Phy-SoC) and application SW development SoC is referred to as application-SoC (App-SoC). Phy-SoC and App-SoC are connected to each other via Ethernet. Ethernet was chosen because of its flexibility, high speed, and easy configuration. For prototyping, we used a LEON3 SoC as the Phy-SoC and a ZYNQ-7000 SoC as the App-SoC. The proposed design was proven in real-time tests and achieved good performance.

• 전자공학회지
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• 제28권4호
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• pp.102.2-103
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• 2001

• 전기학회논문지
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• 제58권7호
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• pp.1418-1423
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• 2009

This paper describes the design and implementation of a System-on-a-Chip (SoC) for image processing applications to use in wearable/mobile products. The target Soc consists of LEON 2 core, AMBA/APB bus-systems and custom-designed controllers. A new FPGA-based prototyping platform is implemented and used for design and verification of the target SoC. To ensure that the implemented SoC satisfies the required performances, an image processing application is performed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
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• pp.59-62
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• 2003

The purpose of this paper is to present how to implement Segment_LCD display using SoC design. The SoC design is achieved by using an ARM_based Excalibur device. The Excalibur device offers an outstanding embedded development platform with ARM922T and FPA. The design in the Excailbur device uses the embedded AR띤 Processor core and the AMBA high-performance bus (AHH) to write to a memory-mapped slave peripheral in the FPGA portion of the device. Here, Segment_LCD is one kind of memory-mapped slave peripherals. In order to Implement the Segment_LCD display based on SoC design, four steps are fellowed. At first, IP modules are made by using Verilog HDL. Secondly, the ARM processor of the Excalibur is programmed using C in ADS (ARM Developer Suite). And in the third step, the whole system is simulated and verified. At last, modules are downloaded to SoCMaster kit. Both Quartus II software and ModelSim5.5e software are the key software tools during the design.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.965-966
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• 2006

As billion transistors system-on-chip (SoC) design becomes a reality, the productivity gap between rapidly increasing design complexity and designer productivity lagging behind is becoming a more serious problem to be solved. To reduce the gap, we present a system that generates executable transaction level models automatically. It speed up the SoC design space exploration process at various abstraction levels.

• IT SoC Magazine
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• 통권14호
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• pp.27-34
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• 2006