• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.21-24
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• 2002

갈수록 복잡해져 가는 시스템을 한번에 하나의 칩까지 완성하기란 쉬운 일이 아니다. 컴퓨터에서 시뮬레이션이 정상적으로 되었다고 해서 완벽한 동작을 보장하는 것도 아니다. 전체 시스템을 검증하는 것도 컴퓨터 시뮬레이션으로는 불가능한 단계에 왔다. 이로 인하여 시스템 전체가 제대로 동작하는지 검증하기 위한 새로운 방법이 요구된다. 이러한 개념으로 접근하고자 하는 것이 본 논문에서 이야기할 플랫폼 기반의 SoC설계이다. 이 논문에서는 임의의 무선통신시스템의 요구사항을 만족할 수 있는 베이스플랫폼 보드의 구조와 설계 시 고려되어야 할 점을 제안한다.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.25 no.11
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• pp.89-96
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• 2007

• Journal of IKEEE
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• v.16 no.4
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• pp.375-381
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• 2012

In this paper, we present an implementation of Viola-Jones algorithm in a multi-core SoC by using skin color information and a parallel processing method. In order to reduce unnecessary operations and improve the detection speed, we adopted a face detection algorithm based on skin color and deleted background image. The algorithm is functionally divided into several parts taking account of the size and the dependency so that the divided functions can be proceeded in parallel. Experiment results in SoC with built-in Cortex-A9 multi core show that it is about 1.8 times faster than the existing algorithm which is not divided.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.6 s.360
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• pp.9-17
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• 2007

This paper shows an implementation of the baseband processor compliant with the IEEE 802.11a standard. Some innovative techniques are proposed to fulfill the mandatory requirements of the standard. For verification and analysis of this design, we use a Platform-based SoC (system on chip) environment. The entire system consists of test-board for the baseband processor chip and the SoC platform for implementing MAC (medium access control).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.924-927
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• 2009

IP reuse technology, for the sake of out-performance and the reduction of development period of IT-SoC is the most essential factor for the sound growth of SoC industry. As for this IP reuse technology, it is very important to decide the proper specification and the standardization of the requirement from the companies, as well as to develop our own domestic technological know-how which does not depend on import. In this study, we propose to analyze a security core IP with pure domestic technological know-how, mentioning an example from $CAST_{TM}$, which presently is an American company costing royalty.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.258-258
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• 2004

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1038-1041
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• 2005

In today's SoC design, most of IPs which use the different clock frequency from that of the bus require asynchronous FIFOs. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, a register-based asynchronous FIFO is designed to transfer data in asynchronous clock domains by using a valid bits scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the gate level to compare with other FIFO scheme.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.05a
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• pp.63-65
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• 2021

This paper describes an integrated H/W-S/W implementation of elliptic curve digital signature algorithm (EC-DSA) using a security system-on-chip (SoC). The security SoC uses the Cortex-A53 APU as CPU, and the hardware IPs of high-performance elliptic curve cryptography (HP-ECC) core and SHA3 (secure hash algorithm 3) hash function core are interfaced via AXI4-Lite bus protocol. The signature generation and verification processes of EC-DSA were verified by the implementation of the security SoC on a Zynq UltraScale+ MPSoC device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.65-73
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• 2007

This paper introduces design-for-test (DFT) techniques for low-cost system-on-chip (SoC) test. We present a Scan-Test method that controls IEEE 1500 wrapper thorough IEEE 1149.1 SoC TAP (Test Access Port) and design an at-speed test clock generator for delay fault test. Test cost can be reduced by using small number of test interface pins and on-chip test clock generator because we can use low-price automated test equipments (ATE). Experimental results evaluate the efficiency of the proposed method and show that the delay fault test of different cores running at different clocks test can be simultaneously achieved.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.2
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• pp.462-469
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• 2008

In this paper, we design the FPGA (Field-Programmable Gate Array) of the KOINONIA WPAN (Wireless Personal Area Network), and implement the SoC (System on Chip). We use the redundant bits to make a constant-amplitude in a modulator part. Additionally, the SNR (Signal to Noise Ratio) performance of the demodulator is improved by using the redundant bits in decoding steps. The four-million FPGA of the KOINONIA WPAN can be operated at 44MHz frequency. The PER (Packet Error Rate) of the designed FPGA with RF (Radio Frequency) module is below 1% at the -86dB MIPLS (Minimum Input Power Level Sensitivity), and the SNR is about 13dB. The SoC is implemented by using Hynix 0.25um CMOS (Complementary Metal Oxide Semiconductor) process. The size of the SoC is $6.52mm{\times}6.92mm$.