• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.4
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• pp.626-631
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• 2019

The policy-making and technological development for the supply expansion of eco-friendly automobiles has been continuing, but the internal combustion engines still accounts for about 95%. Also, in order to meet the stricter emission regulations of internal combustion engines based on fossil fuels, the proportion of after-treatments for vehicles and (ocean going) vessels is gradually increasing. This study is a basic study for the post-Euro-VI exhaust response of CNG buses, and it is to investigate the basic characteristics according to Pd substitution transition metal effect, catalyst volume effect and space velocity. A catalysts was prepared and tested using a model gas reactor. The NGOC catalyst with 3Pd exhibited the highest catalytic activity with 22% at $300^{\circ}C$, 48% at $350^{\circ}C$ and about 75% at $500^{\circ}C$. 3Co NGOC containing 3wt% of transition metal was excellent in oxidation ability, and it was small in size of 2nm, and the degree of catalyst dispersion was improved and de-NO/CO conversion was high. The volume of the NGOC-LNT-SCR catalyst system was optimal in the combination of 1.5+0.5+0.5 with a total score of 165, considering $de-CH_4/NOx$ performance and catalyst cost. For SV $14,000h^{-1}$, the $CH_4$ reduction performance was the highest at about 20%, while the SV $56,000h^{-1}$ was the lowest at about 5%. If the space velocity is small, the flow velocity decreases and the time remaining in the catalyst volume become long, so that the harmful gas was reduced.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.1
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• pp.175-182
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• 2011

In this paper, we implemented a high-performence memory controller which can accommodate processing blocks(multiple masters) in SoC for video signal processing. The memory controller is arbitrated by the internal arbiter which receives request signals from masters and sends grant and data signals to masters. The designed memory controller consists of Master Selector, Mster Arbiter, Memory Signal Generator, Command Decoder, and memory Signal Generator. It was designed using VHDL, and verified using the memory model of SAMSING Inc. For FPGA synthesis and verification, Quartus II of ATERA Inc. was used. The target device is Cyclone II. For simulation, ModelSim of Cadence Inc was used. Since the designed H/W can be stably operated in 174.28MHz, it satisfies the specification of SDRAM technology.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.2
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• pp.95-103
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• 2002

We know that the all of warfare system has been becoming complex and variety in warfield thru the Gulf-War. The all of warfare electronic systems is designed to inter-operate by networks in recently. Especially Warfare Equipment systems of Men-of-War(War ship) as like KDX(Korea Destroyer, Experimental), FF(Frigate), PCC(Costal Patrol Craft), Submarine are connected by Combat System Databus to the Command system(C2 System), so C2 system can control all of equipments in ship. In this view, the status of network(Combat System Databus) is very critical parameter in war field. So In this paper, we propose the method of Network Management System construction for War ship, and especially propose the architectural design of network management system for DX(Destroyer, Experimental) equipments using SNMP(Simple Network Management Protocol). And Link Utilization is monitored by simulation. 

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.54-60
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• 2006

In order to test the board with IEEE 1149.1 boundary scan design, the test sequence must be applied as the bit stream However it is very tedious job to generate the test bit sequence since it requires the complete hlowledge about the 1149.1. This fuper introduces a convenient PCI/USB interface controller, named as Test-Ready PCI (TRPCI) ard Test-Ready USB (TRUSB). Test Bus Controller has been developed by TI and Lucent aiming to generate the test bit stream as an instruction level, thus even the novice test engineer can easily generate the test sequence.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6C
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• pp.498-504
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• 2008

In this paper, an efficient hardware platform for the digital signal processing for OFDM Communication systems is presented. The hardware platform consists of a single FPGA, two DSPs with 8000 MIPS of maximum at 1 GHz clock, 2-channel ADC and DAC supporting maximum 125 MHz sampling rate, and flexible data bus architecture, so that a wide variety of baseband signal processing algorithms for practical OFDM communication systems may be implemented and tested. The IEEE 802.16 software modem is also presented in order to verify the effectiveness and usefulness of the designed platform.

• The Journal of the Korea Contents Association
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• v.6 no.11
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• pp.225-234
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• 2006

In this paper, we design a combined security processor, ECC, MD-5, and AES, as a SIP for cryptography of securing contents. Each SIP is modeled and designed in VHDL and implemented as a reusable macro through logic synthesis, simulation and FPGA verification. To communicate with an ARM9 core, we design a BFM(Bus Functional Model) according to AMBA AHB specification. The combined security SIP for a platform-based SoC is implemented by integrating ECC, AES and MD-5 using the design kit including the ARM9 RISC core, one million-gate FPGA. Finally, it is fabricated into a MPW chip using Magna chip $0.25{\mu}m(4.7mm{\times}4.7mm$) CMOS technology.

• Journal of the Korean Society for Precision Engineering
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• v.10 no.4
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• pp.227-235
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• 1993

In this paper, the development of a high performance flexible controller is described. The hardware of the controller, based on VME-bus, consists of four M68020 single-board computers (32-bit) with M68881 numerical coprocessors, two M68040 single board donputers, I/O devices (such as A/D and D/A converters, paraller I/O, encoder counters), and bus-to-bus adaptor. This software, written in C and based on X-window environment with Unix operating system, includes : text editor, compiler, downloader, and plotter running in a host computer for developing control program ; device drivers, scheduler, and mathemetical routines for the real time control purpose ; message passing, file server, source level debugger virtural terminal, etc. The hardware and software are structured so that the controller might have both flexibility and extensibility. In papallel to the controller, a three degrees of freedom kinematically redundant robot has been developed at the same time. The development of the same time. The development of the robot was undertaken in order to provide, on the one hand, a computationally intensive plant to which to apply the controller, and on the other hand a research tool in the field of kinematically redundant manipulator, which is, as such, an important area. By using the controller, dynamic control of the redundant manipulator was successfully experimented, showing the effectiveness and flexibility of the controller.

• The KIPS Transactions:PartC
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• v.13C no.7 s.110
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• pp.881-888
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• 2006

The position of the bridged tap is determined by that of the outlet in most modern apartments, since most of the indoor wiring utilizes the bus wiring structure when deploying the indoor communication line. These bridged taps deteriorate transmission performance in the specific frequency at the time of high-speed multimedia communication, which uses a high frequency bandwidth, since the duality of return loss worsens and line attenuation increases rapidly. As a result, analysis on this phenomenon is required. In this study, the test model is created by modeling the intercommunication facility of the apartment that is the most representative residential house type, and by understanding the structure and the environment of the indoor wiring. Also, how the bridge tap affects performance is analyzed when the VDSL service is provided, so that problems of intercommunication lines can be identified and methods for improving the proper intercommunication line can be suggested, which is suitable for accommodating high-speed multimedia service of the future.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.9-17
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• 2006

We proposed a new High-speed CMOS Level Up/Down Shifter circuits that can be used with Dynamic Voltage and Frequency Scaling(DVFS) algorithm, for low power system in the SoC(System-on-Chip). This circuit used to interface between the other voltage levels in each CMOS circuit boundary, or between multiple core voltage levels in a system bus. Proposed circuit have advantage that decrease speed attenuation and duty ratio distortion problems for interface. The level up/down shifter of the proposed circuit designed that operated from multi core voltages$(0.6\sim1.6V)$ to used voltage level for each IP at the 500MHz input frequency The proposed circuit supports level up shifting from the input voltage levels, that are standard I/O voltages 1.8V, 2.5V, 3.3V, to multiple core voltage levels in between of $0.6V\sim1.6V$, that are used internally in the system. And level down shifter reverse operated at 1Ghz input frequency for same condition. Simulations results are shown to verify the proposed function by Hspice simulation, with $0.6V\sim1.6V$ CMOS Process, $0.13{\mu}m$ IBM CMOS Process and $0.65{\mu}m$ CMOS model parameters. Moreover, it is researched delay time, power dissipation and duty ration distortion of the output voltage witch is proportional to the operating frequency for the proposed circuit.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.30 no.4D
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• pp.403-411
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• 2010

Nowadays, Light railway system is attracted public attention as solution for metropolitan traffic congestion. But it is difficult to decide an appropriate light railway system. It is especially hard in the Seoul metropolitan to decide an appropriate system, because there are many factors that must considered. So we research application status of light railway system that is scheduled or promoted in the Korea and the foreign nations. And we selected systems by types of city. In this paper, we divided into 6 types of city through factor analysis and cluster. And we considered various factor such as technology, transportation, environment etc that used previous research and feasibility study. To determine the priority among the factors, AHP(Analytic Hierarchy Process) was applied as a method for multi-standard decision method.