• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.82-82
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• 2007

The chemical mechanical polishing (CMP) process has been widely used to obtain global planarization of multilevel interconnection process for ultra large scale. integrated circuit applications. Especially, the application of copper CMP has become an integral part of several semiconductor device and materials manufacturers. However, the low-k materials at 65nm and below device structures because of fragile property, requires low down-pressure mechanical polishing for maintaining the structural integrity of under layer during their fabrication. In this paper, we studied electrochemical mechanical polishing (ECMP) as a new planarization technology that uses electrolyte chemistry instead of abrasive slurry for copper CMP process. The current-voltage (I-V) curves were employed we investigated that how this chemical affect the process of voltage induced material removal in ECMP of Copper. This work was supported by grant No. (R01-2006-000-11275-0) from the Basic Research Program of the Korea Science.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.5
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• pp.301-306
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• 2017

Wire electrical discharge machining (WEDM) process was evaluated to slice Silicon (Si) for various applications. Specifically, various Si workpieces with various resistances, such as single and multi crystalline Si bricks and wafers were used. As conventional slicing processes, such as slurry-on or diamond-on wire slicing, are based on mechanical abrasions between Si and abrasive, there is a limitation to decrease the wafer thickness as well as kerf-loss. Especially, when the wafer thickness is less than $150{\mu}m$, wafer breakage increases dramatically during the slicing process. Single crystalline P-type Si bricks and wafers were successively sliced with considerable slicing speed regardless of its growth direction. Also, typical defects, such as microcracks, craters, microholes, and debris, were introduced when Si was sliced by electrical discharge. Also, it was found that defect type is also dependent on resistance of Si. Consequently, this study confirmed the feasibility of slicing single crystalline Si by WEDM.

• Tribology and Lubricants
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• v.32 no.4
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• pp.119-124
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• 2016

In the sapphire wafering process, lapping is a crucial operation in order to reduce the damaged layer and achieve the target thickness. Many parameters, such as pressure, velocity, abrasive, slurry and plate, affect lapping characteristics. This paper presents an experimental investigation on the effect of the plate groove on the material removal rate and roughness of the wafer. We select the spiral pattern and rectangular type as the groove shapes. We vary the groove density by controlling the groove shape dimension, i.e., the groove width and pitch. As the groove density increases to 0.4, the material removal rate increases and gradually reaches a saturation point. When the groove density is low, the pressing load is mostly supported by the thick film, and only a small amount acts on the abrasives resulting to a low material removal rate. The roughness decreases on increasing the groove density up to 0.3 because thick film makes partial participations of large abrasives which make deep scratches. From these results, we could conclude that the groove affects the contact condition between the wafer and plate. At the same groove density, the pitch has more influence on reducing the film thickness than the groove width. By decreasing the groove density with a smaller pitch and larger groove width, we could achieve a high material removal rate and low roughness. These results would be helpful in understanding the groove effects and determining the appropriate groove design.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.545-545
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• 2008

Poly-Si is an essential material for floating gate in NAND Flash memory. To fabricate this material within region of floating gate, chemical mechanical polishing (CMP) is commonly used process for manufacturing NAND flash memory. We use colloidal silica abrasive with alkaline agent, polymeric additive and organic surfactant to obtain high Poly-Si to SiO2 film selectivity and reduce surface defect in Poly-Si CMP. We already studied about the effects of alkaline agent and polymeric additive. But the effect of organic surfactant in Poly-Si CMP is not clearly defined. So we will examine the function of organic surfactant in Poly-Si CMP with concentration separation test. We expect that surface roughness will be improved with the addition of organic surfactant as the case of wafering CMP. Poly-Si wafer are deposited by low pressure chemical vapor deposition (LPCVD) and oxide film are prepared by the method of plasma-enhanced tetra ethyl ortho silicate (PETEOS). The polishing test will be performed by a Strasbaugh 6EC polisher with an IC1000/Suba IV stacked pad and the pad will be conditioned by ex situ diamond disk. And the thickness difference of wafer between before and after polishing test will be measured by Ellipsometer and Nanospec. The roughness of Poly-Si film will be analyzed by atomic force microscope.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.565-566
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• 2006

Slurry used in metal chemical mechanical polishing normally consists of an oxidizer, a complexing agent, a corrosion inhibitor and an abrasive. This paper investigates effects of citric acid as a complexing agent for Cu CMP with $H_2O_2$ as an oxidizer. In order to study chemical effects of a citric acid, x-ray photoelectron spectroscopy were performed on Cu sample after Cu etching test. XPS results reveal that CuO, $Cu(OH)_2$ layer decrease but Cu/$Cu_2O$ layer increase on Cu sample surface. To investigate nanomechanical properties of Cu sample surface, nanoindentation was performed on Cu sample. Results of nanoindentation indicate wear resistance of Cu Surface decrease. According to decrease of wear resistance on Cu surface, removal rate increases from $285\;{\AA}/min$ to $8645\;{\AA}/min$ in Cu CMP.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.29 no.6
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• pp.383-388
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• 2019

High purity SiC fine powder with metal impurity contents of less than 1 ppm was synthesized by improved carbothermal reduction process, and the synthesized powder was used for SiC single crystal growth in RF heating PVT device at temperature above 2,100℃. In-situ x-ray image analyzer was used to observe the sublimation of the powder and single crystal growth behavior during the growth process. SiC powder was used as a source of single crystal growth, exhausted from the outside of the graphite crucible at the growth temperature and left graphite residues. During the growth, the flow of raw materials was concentrated in the middle and influenced the growth behavior of SiC single crystals. This is due to the difference in temperature distribution inside the crucible due to the fine powder. After the single crystal growth was completed, the single crystal ingot was cut into a 1 mm thick single crystal substrate and finely polished using a diamond abrasive slurry. A dark yellow 4H-SiC was observed overall of single crystal substrate, and the polycrystals generated in the outer part may be caused by the incorporation of impurities such as the bubble layer mixed in the process of attaching the seed crystal to the seed holder.