• Journal of Communications and Networks
• /
• v.8 no.1
• /
• pp.8-12
• /
• 2006

Master-slave (M-S) strategies implemented with chain circuits are the main option in order to distribute clock signals along synchronous networks in several telecommunication and control applications. Here, we study the two types of masterslave chains: Without clock feedback, i.e., one-way master-slave (OWMS) and with clock feedback, i.e., two-way master-slave (TWMS) considering the slave nodes as second-order phase-locked loops (PLL) for several types of loop low-pass filters.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.12B
• /
• pp.1037-1041
• /
• 2004

In this paper we propose a new conceptual slave clock system in which remotely located clock is synchronized to the reference clock by intermediation of the satellite time, show a probability of adoption to real network by experiments. This new proposed method has lots of structural advantages over the existing methods because all of the node clocks can be maintained with the same hierarchical quality. The measurement results show that the accuracy of the experimental slave clock system can be kept within a few parts in 1012 and that the MTIE (Maximum Time Interval Error) meets the ITU-T Recommendation G.811 for the primary reference clock A prototype system having fully automatic operational functions has been realized, and it is expected to be commercially used as a node clock for synchronization in the digital communication network in the near future.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.865-868
• /
• 2005

This paper presents a Clock-gating technique that reduces power dissipation of the sequential circuits in the system. The Master Clock of a Clock-gating technique is formed by a quaternary variable. It uses the covering relationship between the triggering transition of the clock and the active cycles of various flip-flops to generate a slave clock for each flip-flop in the circuit. At current RTL designs flip-flop is acted by Master clock's triggering but the Slave Clock of Clock-gating technique doesn't occur trigger when external input conditions have not matched with a condition of logic table. We have applied our clocking technique to UART controller of 8bit microprocess

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.58 no.1
• /
• pp.199-202
• /
• 2009

Scan design is currently the most widely used structured Design For Testability approach. In scan design, all storage elements are replaced with scan cells, which are then configured as one or more shift registers(also called scan chains) during the shift operation. As a result, all inputs to the combinational logic, including those driven by scan cells, can be controlled and all outputs from the combinational logic, including those driving scan cells, can be observed. The scan inserted design, called scan design, is operated in three modes: normal mode, shift mode, and capture mode. Circuit operations with associated clock cycles conducted in these three modes are referred to as normal operation, shift operation, and capture operation, respectively. In spite of these, scan design methodology has defects. They are power dissipation problem and test time during test application. We propose a new methodology about scan shift clock operation and present low power scan design and short test time.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.42 no.1
• /
• pp.61-66
• /
• 2005

Location Positioning is a major technology for ubiquitous computing. Recently the research on Location Positioning using UWB is on going. In order to construct an in-door location network, synchronization of base stations is very important. NTP is Popularly used as clock synchronization protocol ranging from LAN to WAN. Also Master-Slave scheme is the simplest method to synchronize in-door network. We compare and analyze NTP and Master-Slave schemes according to the statistical channel model for indoor multipath propagation environment. In this paper, error ranges are calculated at various circumstances that in-door network expands from one primary base station into several base stations. We compared the correctness of NTP and Master-Slave synchronization methods. NTP is more reasonable synchronization protocol in in-door environment.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
• /
• v.3 no.2
• /
• pp.11-17
• /
• 2004

In this paper we propose a new conceptual system for a network clock in which all node clocks are simultaneously synchronized to the national standard by intermediation parameter of satellite time. Experiments have shown the possibility of its adoption by real networks. The new proposed method has various structural benefits, in particular all node clocks can be kept at the same hierarchical quality in contrast to the existing method. The measurement results show that the accuracy of the experimental slave clock system can be kept within a few parts In 1012 and the MTIE (Maximum Time Interval Error) sufficiently meets ITU-T G.811 for the primary reference clock. A prototype system with fully automatic operational functions has been realized at present and is expected to be directly used for communication network synchronization in the near future.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.11 no.4
• /
• pp.331-339
• /
• 2018

The IEEE 1588, commonly known as a precision time protocol (PTP), is a standard for precise clock synchronization that maintains networked measurements and control systems. The best master clock (BMC) algorithm is currently used to establish the master-slave hierarchy for PTP. The BMC allows a slave clock to automatically take over the duties of the master when the slave is disconnected due to a link failure and loses its synchronization; the slave clock depends on a timer to compensate for the failure of the master. However, the BMC algorithm does not provide a fast recovery mechanism in the case of a master failure. In this paper, we propose a technique that combines the IEEE 1588 with network bonding to provide a faster recovery mechanism in the case of a master failure. This technique is implemented by utilizing a pre-existing library PTP daemon (Ptpd) in Linux system, with a specific profile of the IEEE 1588 and it's controlled through bonding modes. Network bonding is a process of combining or joining two or more network interfaces together into a single interface. Network bonding offers performance improvements and redundancy. If one link fails, the other link will work immediately. It can be used in situations where fault tolerance, redundancy, or load balancing networks are needed. The results show combining IEEE 1588 with network bonding enables an incredible shorter recovery time than simply just relying on the IEEE 1588 recovery method alone.

• Journal of Power Electronics
• /
• v.12 no.6
• /
• pp.886-894
• /
• 2012

This paper presents a secondary-side, dual-mode feedback LLC resonant controller IC with dynamic PWM dimming for LED backlight units. In order to reduce the cost, master and slave outputs can be generated simultaneously with a single LLC resonant core based on dual-mode feedback topologies. Pulse Frequency Modulation (PFM) and Pulse Width Modulation (PWM) schemes are used for the master stage and slave stage, respectively. In order to guarantee the correct dual feedback operation, Phased-Locked Loop (PLL)-based automatic duty control circuit is proposed in this paper. The chip is fabricated using $0.35{\mu}m$ Bipolar-CMOS-DMOS (BCD) technology, and the die size is $2.5mm{\times}2.5mm$. The frequency of the gate driver (GDA/GDB) in the clock generator ranges from 50 to 425 kHz. The current consumption of the LLC resonant controller IC is 40 mA for a 100 kHz operation frequency using a 15 V supply. The duty ratio of the slave stage can be controlled from 40% to 60% independent of the frequency of the master stage.

• Journal of Institute of Control, Robotics and Systems
• /
• v.20 no.6
• /
• pp.669-675
• /
• 2014

In this paper, we described the investigated theoretical time synchronization performances and experiment results obtained by commercially provided PTP (Precise Time Protocol) modules when the time of a slave clock is synchronized to the master clock. In the case of the theoretical performance analysis, we investigated 3 types of clock levels such as Crystal Oscillator (XO), TCXO (Temperature Compensated XO) and OCXO (Oven Controlled XO). From the analysis, it was observed that the synchronization performance is greatly influenced by the synchronization period and the required performance under 1 us can be achieved by using XO level clocks when the synchronization period is less than 2 seconds and the uncertainty of the propagation delay is under 100 ns. For the experiments using commercial PTP modules, the synchronization performance was investigated for direct, through 1 hub and through 2 hubs connections between the master clock and the slave clock. From the experiment results, we observed that time synchronization under 90 ns with 1,000 seconds observation interval can be achieved in the case of direct connection.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.25 no.2
• /
• pp.259-266
• /
• 2021

USB bus not only works with convenience but also transmits data fast and becomes a standard peripheral interface between FPGA development board and personal computer. In this paper FPGA verification system with slave FIFO interface for Cypress FX3 USB 3 bridge chip was implemented. The designed slave FIFO interface consists of host interface module based on FIFO structure, master bus controller and command decoder and supports streaming communication interface for FX3 bridge chip and memory-mapped input and output interface for user design circuit. The ZestSC3 board with Cypress FX3 USB 3 bridge chip and Xilinx Artix FPGA(XC7A35T-1C5G3241) was used to implement FPGA verification system. It was verified that the FPGA verification system for user design circuit operated correctly under various clock frequencies using GUI software developed by visual C# and C++ DLL. The designed slave FIFO interface for FPGA verification system has modular structure and can be applicable to the different user designs with memory-mapped I/O interface.