• Title/Summary/Keyword: Single-port RAM

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Role of Single Port Rigid Thoracoscopy in Undiagnosed Pleural Effusion

  • Jagdish Rawat;Anil Kumar;Parul Mrigpuri;Dev Singh Jangpangi;Abhay Pratap Singh;Ritisha Bhatt
    • Tuberculosis and Respiratory Diseases
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    • v.87 no.2
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    • pp.194-199
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    • 2024
  • Background: In recent years, medical thoracoscopy has been well established to play an important role in undiagnosed pleural effusion; however, this procedure is underutilized due to limited availability of the instruments it requires. This study analysed the outcome of single port rigid thoracoscopy in patients with undiagnosed pleural effusions. Methods: This study retrospectively analysed the outcomes of all patients with undiagnosed pleural effusion presenting to our centre between 2016 to 2020 who underwent single port rigid medical thoracoscopy as a diagnostic procedure. Results: In total, 92 patients underwent single port rigid medical thoracoscopy. The most common presenting symptom was shortness of breath. A majority of the patients had lymphocytic exudative pleural effusion. The average biopsy sample size was 18 mm, and no major complication was reported in any of the patients. Conclusion: Single port rigid thoracoscopy is a safe and well-tolerated procedure that yields a biopsy of a larger size with high diagnostic yield. Moreover, the low cost of the instruments required by this procedure makes it particularly suited for use in developing countries.

Automation of Supervision Device by the Data Logger in Distribution System (배전계통에서 Data Logger에 의한 감시장치의 자동화)

  • 문학룡;김진상;김수곤;전희종
    • The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.10 no.3
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    • pp.64-70
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    • 1996
  • In this paper, we designed a low cost data logger system using single chip microcontroller. It detects the normal and abnormal current in distribution system. A sampled analog signals are stored on RAM card(4Mbit) after digitalized by internal A/D converter. Stored data can be transmitted to the personal computer either by internal serial communication port or by external parallel communication port. The transmitted data are analyzed and displayed on personal computer.

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Analysis of the Image Processing Speed by Line-Memory Type (라인메모리 유형에 따른 이미지 처리 속도의 분석)

  • Si-Yeon Han;Semin Jung;Bongsoon Kang
    • Journal of IKEEE
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    • v.27 no.4
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    • pp.494-500
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    • 2023
  • Image processing is currently used in various fields. Among them, autonomous vehicles, medical image processing, and robot control require fast image processing response speeds. To fulfill this requirement, hardware design for real-time processing is being actively researched. In addition to the size of the input image, the hardware processing speed is affected by the size of the inactive video periods that separate lines and frames in the image. In this paper, we design three different scaler structures based on the type of line memories, which is closely related to the inactive video periods. The structures are designed in hardware using the Verilog standard language, and synthesized into logic circuits in a field programmable gate array environment using Xilinx Vivado 2023.1. The synthesized results are used for frame rate analysis while comparing standard image sizes that can be processed in real time.

Design of High Speed VRAM ASIC for Image Signal Processing (영상 신호처리를 위한 고속 VRAM ASIC 설계)

  • Seol, Wook;Song, Chang-Young;Kim, Dae-Soon;Kim, Hwan-Yong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.6
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    • pp.1046-1055
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    • 1994
  • In this paper, to design high speed 1 line VRAM(Video RAM) suitable for image signal processing with ASIC(Application Specific IC) method, the VRAM memory core has been designed using 3-TR dual-port dynamic cell which has excellent access time and integration characteristics. High speed pipeline operation was attained by separating the first row from the subarray 1 memory core and the simultaneous I/Q operation for a selected single address was made possible by adopting data-latch scheme. Peripheral circuits were designed implementing address selector and 1/2V voltage generator. Integrated ASIC has been optimized using 1.5[ m] CMOS design rule.

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