• Title/Summary/Keyword: Single-chip

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A study on the digital carrier recovery loop with adaptive loop bandwidth (적응 루프 대역폭을 가진 디지털 반송파 동기 루프에 관한 연구)

  • 한동석
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.22 no.8
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    • pp.1774-1781
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    • 1997
  • In this paper, we propose a full digital frequency and phase locked loop for CATV and HDTV receivers adopting VSB modulation. The CATV and HDTV receivers proposed by the Grand-Alliance in USA are ultilizing analog signal processing technology for carrier recovery. By the way, it is not a good architecture for the development of single chip ASIC operating in digital domain. To solve this problem while improving the performance, we first down convert the received r.f. signal to a near baseband signal for a low-rate AD converter and then we use digital signal processing techniques. The proposed system has the frequency pull-in range of -200 KHz +2.50 KHz. Moreover, it has the ability of adaptive loop bandwidth control according to the amount of frequency offset to improve the acquisition time while reducing the phase noise.

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A whole genomic scan to detect selection signatures between Berkshire and Korean native pig breeds

  • Edea, Zewdu;Kim, Kwan-Suk
    • Journal of Animal Science and Technology
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    • v.56 no.7
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    • pp.23.1-23.7
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    • 2014
  • Background: Scanning of the genome for selection signatures between breeds may play important role in understanding the underlie causes for observable phenotypic variations. The discovery of high density single nucleotide polymorphisms (SNPs) provide a useful starting point to perform genome-wide scan in pig populations in order to identify loci/candidate genes underlie phenotypic variation in pig breeds and facilitate genetic improvement programs. However, prior to this study genomic region under selection in commercially selected Berkshire and Korean native pig breeds has never been detected using high density SNP markers. To this end, we have genotyped 45 animals using Porcine SNP60 chip to detect selection signatures in the genome of the two breeds by using the $F_{ST}$ approach. Results: In the comparison of Berkshire and KNP breeds using the FDIST approach, a total of 1108 outlier loci (3.48%) were significantly different from zero at 99% confidence level with 870 of the outlier SNPs displaying high level of genetic differentiation ($F_{ST}{\geq}0.490$). The identified candidate genes were involved in a wide array of biological processes and molecular functions. Results revealed that 19 candidate genes were enriched in phosphate metabolism (GO: 0006796; ADCK1, ACYP1, CAMK2D, CDK13, CDK13, ERN1, GALK2, INPP1; MAK, MAP2K5, MAP3K1, MAPK14, P14KB, PIK3C3, PRKC1, PTPRK, RNASEL, THBS1, BRAF, VRK1). We have identified a set of candidate genes under selection and have known to be involved in growth, size and pork quality (CART, AGL, CF7L2, MAP2K5, DLK1, GLI3, CA3 and MC3R), ear morphology and size (HMGA2 and SOX5) stress response (ATF2, MSRB3, TMTC3 and SCAF8) and immune response (HCST and RYR1). Conclusions: Some of the genes may be used to facilitate genetic improvement programs. Our results also provide insights for better understanding of the process and influence of breed development on the pattern of genetic variations.

Implementation of a Shared Buffer ATM Switch Embedded Scalable Pipelined Buffer Memory (가변형 파이프라인방식 메모리를 내장한 공유버퍼 ATM 스위치의 구현)

  • 정갑중
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.6 no.5
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    • pp.703-717
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    • 2002
  • This paper illustrates the implementation of a scalable shared buffer asynchronous transfer mode (ATM) switch. The designed shared buffer ATM switch has a shared buffet of a pipelined memory which has the access time of 4 ns. The high-speed buffer access time supports a possibility of the implementation of a shared buffer ATM switch which has a large switching capacity. The designed switch architecture provides flexible switching performance and port size scalability with the independence of queue address control from buffer memory control. The switch size and the buffer size of the designed ATM switch can be reconfigured without serious circuit redesign. The designed prototype chip has a shared buffer of 128-cell and 4 ${\times}$ 4 switch size. It is integrated in 0.6um, double-metal, and single-poly CMOS technology. It has 80MHz operating frequency and supports 640Mbps per port.

A Study on 16 bit EISC Microprocessor (16 비트 EISC 마이크로 프로세서에 관한 연구)

  • 조경연
    • Journal of Korea Multimedia Society
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    • v.3 no.2
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    • pp.192-200
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    • 2000
  • 8 bit and 16 bit microprocessors are widely used in the small sited control machine. The embedded microprocessors which is integrated on a single chip with the memory and I/O circuit must have simple hardware circuit and high code density. This paper proposes a 16 bit high code density EISC(Extendable Instruction Set Computer) microprocessor. SE1608 has 8 general purpose registers and 16 bit fixed length instruction set which has the short length offset and small immediate operand. By using an extend register and extend flag, the offset and immediate operand in instruction could be extended. SE1608 is implemented with 12,000 gate FPGA and all of its functions have been tested and verified at 8MHz. And the cross assembler, the cross C/C++compiler and the instruction simulator of the SE1608 have been designed and verified. This paper also proves that the code density$.$ of SE1608 shows 140% and 115% higher code density than 16 bit microprocessor H-8300 and MN10200 respectively, which is much higher than traditional microprocessors. As a consequence, the SE1608 is suitable for the embedded microprocessor since it requires less program memory to any other ones, and simple hardware circuit.

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A Design of 10bit current output Type Digital-to-Analog converter with self-Calibration Techique for high Resolution (고해상도를 위한 DAC 오차 보정법을 가진 10-비트 전류 출력형 디지털-아날로그 변환기 설계)

  • Song, Jung-Gue;Shin, Gun-Soon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.4
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    • pp.691-698
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    • 2008
  • This paper describes a 3.3V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method with monotonicity, glitch energy. The output stage utilizes here implements a return-to-zero circuit to obtain the dynamic performance. Most of D/A converters in decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. the designed D/A converter using the CMOS n-well $0.35{\mu}m$ process0. The experimental data shows that the rise/fall time, settling time, and INL/DNL are 1.90ns/2.0ns, 12.79ns, and a less than ${\pm}2.5/{\pm}0.7\;LSB$, respectively. The power dissipation of the D/A converter with a single power supply of 3.3V is about 250mW.

A Design of Multimedia Application SoC based with Processor using BTB (BTB를 이용한 프로세서 기반 멀티미디어 응용 SoC 설계)

  • Jung, Younjin;Lee, Byungyup;Ryoo, Kwangki
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2009.10a
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    • pp.397-400
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    • 2009
  • This paper describes ASIC design of Multimedia application SoC platform based RISC processor with BTB(Branch Target Buffer). For performance enhancement of platform, we use a simple branch prediction scheme, BTB structure, that stores a target address for branch instruction to remove pipeline harzard. Also, the platform includes a number of peripheral such as VGA controller, AC97 controller, UART controller, SRAM interface and Debug interface. The platform is designed and verified on a Xilinx VERTEX-4 FPGA using a number of test programs for functional tests and timing constraints. Finally, the platform is implemented into a single ASIC chip which can be operated at 100MHz clock frequency using the Chartered 0.18um process. As a result of performance estimation, the proposed platform shows about 5~9% performance improvement in comparison with the previous SoC Platform.

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Wireless operational modal analysis of a multi-span prestressed concrete bridge for structural identification

  • Whelan, Matthew J.;Gangone, Michael V.;Janoyan, Kerop D.;Hoult, Neil A.;Middleton, Campbell R.;Soga, Kenichi
    • Smart Structures and Systems
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    • v.6 no.5_6
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    • pp.579-593
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    • 2010
  • Low-power radio frequency (RF) chip transceiver technology and the associated structural health monitoring platforms have matured recently to enable high-rate, lossless transmission of measurement data across large-scale sensor networks. The intrinsic value of these advanced capabilities is the allowance for high-quality, rapid operational modal analysis of in-service structures using distributed accelerometers to experimentally characterize the dynamic response. From the analysis afforded through these dynamic data sets, structural identification techniques can then be utilized to develop a well calibrated finite element (FE) model of the structure for baseline development, extended analytical structural evaluation, and load response assessment. This paper presents a case study in which operational modal analysis is performed on a three-span prestressed reinforced concrete bridge using a wireless sensor network. The low-power wireless platform deployed supported a high-rate, lossless transmission protocol enabling real-time remote acquisition of the vibration response as recorded by twenty-nine accelerometers at a 256 Sps sampling rate. Several instrumentation layouts were utilized to assess the global multi-span response using a stationary sensor array as well as the spatially refined response of a single span using roving sensors and reference-based techniques. Subsequent structural identification using FE modeling and iterative updating through comparison with the experimental analysis is then documented to demonstrate the inherent value in dynamic response measurement across structural systems using high-rate wireless sensor networks.

The influence of a first-order antedependence model and hyperparameters in BayesCπ for genomic prediction

  • Li, Xiujin;Liu, Xiaohong;Chen, Yaosheng
    • Asian-Australasian Journal of Animal Sciences
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    • v.31 no.12
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    • pp.1863-1870
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    • 2018
  • Objective: The Bayesian first-order antedependence models, which specified single nucleotide polymorphisms (SNP) effects as being spatially correlated in the conventional BayesA/B, had more accurate genomic prediction than their corresponding classical counterparts. Given advantages of $BayesC{\pi}$ over BayesA/B, we have developed hyper-$BayesC{\pi}$, ante-$BayesC{\pi}$, and ante-hyper-$BayesC{\pi}$ to evaluate influences of the antedependence model and hyperparameters for $v_g$ and $s_g^2$ on $BayesC{\pi}$.Methods: Three public data (two simulated data and one mouse data) were used to validate our proposed methods. Genomic prediction performance of proposed methods was compared to traditional $BayesC{\pi}$, ante-BayesA and ante-BayesB. Results: Through both simulation and real data analyses, we found that hyper-$BayesC{\pi}$, ante-$BayesC{\pi}$ and ante-hyper-$BayesC{\pi}$ were comparable with $BayesC{\pi}$, ante-BayesB, and ante-BayesA regarding the prediction accuracy and bias, except the situation in which ante-BayesB performed significantly worse when using a few SNPs and ${\pi}=0.95$. Conclusion: Hyper-$BayesC{\pi}$ is recommended because it avoids pre-estimated total genetic variance of a trait compared with $BayesC{\pi}$ and shortens computing time compared with ante-BayesB. Although the antedependence model in $BayesC{\pi}$ did not show the advantages in our study, larger real data with high density chip may be used to validate it again in the future.

The design and development of Control/Storage and TRX Module for Small Satellite Synthetic Aperture Radar Application (초소형위성 영상레이다를 위한 제어/저장 및 송수신 모듈의 설계 및 제작)

  • Lee, Juyoung;Kim, Hyunchul;Kim, Jongpil;Yu, Kyungdeok;Kim, Dongsik
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.22 no.6
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    • pp.31-36
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    • 2022
  • In this paper, we present the design, manufacture and test results of Backend unit for SAR(Synthetic Aperture Radar) that can be applied on a small satellite. The Backend unit for SAR was designed with a control/storage board, TRX(transmission and receiving) board and a power supply board as a single unit in consideration of the applying of a small satellite. The control/storage board uses RFSoC to generate wideband chirp signal, generate operating timings, and perform control and calculations for SAR operation. The TRX board is designed to convert the wideband chirp signal generated by the control/storage board to the operating frequency of X-band by up-converting the frequency. Since small size, light weight, and low cost are important consideration for small satellite, MIL/Industrial grade components were appropriately applied and the at the same time it was designed to ensure mission life through the radiation test, analysis and space environment tests.

Characterization analysis of Rongchang pig population based on the Zhongxin-1 Porcine Breeding Array PLUS

  • Dong Leng;Liangpeng Ge;Jing Sun
    • Animal Bioscience
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    • v.36 no.10
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    • pp.1508-1516
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    • 2023
  • Objective: To carry out a comprehensive production planning of the existing Rongchang pig population from both environmental and genetic aspects, and to establish a closed population with stable genetic diversity and strict pathogen control, it is necessary to fully understand the genetic background of the population. Methods: We genotyped 54 specific pathogen free (SPF) Rongchang pigs using the Zhongxin-1 Porcine Breeding Array PLUS, calculated their genetic diversity parameters and constructed their families. In addition, we also counted the runs of homozygosity (ROH) of each individual and calculated the value of inbreeding coefficient based on ROH for each individual. Results: Firstly, the results of genetic diversity analysis showed that the effective population size (Ne) of this population was 3.2, proportion of polymorphic markers (PN) was 0.515, desired heterozygosity (He) and observed heterozygosity (Ho) were 0.315 and 0.335. Ho was higher than He, indicating that the heterozygosity of all the selected loci was high. Secondly, combining the results of genomic relatedness analysis and cluster analysis, it was found that the existing Rongchang pig population could be divided into four families. Finally, we also counted the ROH of each individual and calculated the inbreeding coefficient value accordingly, whose mean value was 0.09. Conclusion: Due to the limitation of population size and other factors, the genetic diversity of this Rongchang pig population is low. The results of this study can provide basic data to support the development of Rongchang pig breeding program, the establishment of SPF Rongchang pig closed herd and its experimental utilization.