• 한국전산유체공학회:학술대회논문집
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• 2004.10a
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• pp.173-176
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• 2004

In this study, the multidisciplinary aerodynamic-structural optimal design is carried out for the supersonic fighter wing. Through the aeroelastic analyses of the various candidate wings, the aerodynamic and structural performances are calculated such as the lift coefficient, the drag coefficient and the deformation of the wing. In general, the supersonic fighter is maneuvered under the various flight conditions and those conditions must be considered all together during the design process. The multi-point design, therefore, is deemed essential. For this purpose, supersonic dash, long cruise range and high angle of attack maneuver are selected as representative design points. Based on the calculated performances of the candidate wings, the response surfaces for the objectives and constraints are generated and the supersonic fighter wing is designed for better aerodynamic performances and less weights than the baseline. At each design point, the single-point design is performed to obtain better performances. Finally, the multi-point design is performed to improve the aerodynamic and structural performances for all design points. The optimization results of the multi-point design are compared with those of the single-point designs and analyzed in detail.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.778-780
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• 1999

Arithmetic unit speed depends strongly on the algorithms employed to realize the basic arithmetic operations.(add, subtract multiply, and divide) and on the logic design. Recent advances in VLSI have increased the feasibility of hardware implementation of floating point arithmetic units and microprocessors require a powerful floating-point processing unit as a standard option. This paper describes the design of floating-point multiplier for IEEE 754-1985 Single-Precision operation. Booth encoding algorithm method to reduce partial products and a Wallace tree of 4-2 CSA is adopted in fraction multiplication part to generate the $32{\times}32$ single-precision product. New scheme of rounding and sticky-bit generation is adopted to reduce area and timing. Also there is a true sign generator in this design. This multiplier have been implemented in a ALTERA FLEX EPF10K70RC240-4.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.30 no.8 s.251
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• pp.889-896
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• 2006

The concept of reliability has been applied to the topology optimization based on a reliability index approach or a performance measure approach. Since these approaches, called double-loop single vector approach, require the nested optimization problem to obtain the most probable point in the probabilistic design domain, the time for the entire process makes the practical use infeasible. In this work, new reliability-based topology optimization method is proposed by utilizing single-loop single-vector approach, which approximates searching the most probable point analytically, to reduce the time cost. The results of design examples show that the proposed method provides efficiency curtailing the time for the optimization process and accuracy satisfying the specified reliability.

• 한국전산유체공학회:학술대회논문집
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• 2003.10a
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• pp.240-242
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• 2003

A method for performing two-dimensional lift-constraint drag minimization in inviscid compressible flows on unstructured meshes is developed. Sensitivities of objective function with respect to the design variables are efficiently obtained by using a continuous adjoint method. In addition, parallel algorithm is used in multi-point design optimization to enhance the computational efficiency. The characteristics of single-point and multi-point optimization are examined, and the comparison of these two method is presented.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.301-304
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• 2000

In this paper, we designed a 256-point FFT processor using VHDL. We adopted Radix-2$^2$SDC(Single-path Delay Commutator) architectures to reduce the number of complex multipliers. We confirmed the operation of the design through simulation using Altera MAX+PLUS II.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.05a
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• pp.1115-1116
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• 2010

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.9
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• pp.773-778
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• 2014

Aircraft communication system which provides internal communications between pilots in an aircraft and external communications between pilots and operators in ground tower with them. It is very important equipment in terms of mission and safety. It wouldn't meet performance requirements with only functions of transmission and receiving of signals. It should provide highly clear voice quality without any noise. This paper analyzes the cause of noise during internal communications and summarizes the design changes applying single point ground concept to solve the problem. It also describes the results of fight test to verify the design changes.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.18 no.1
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• pp.51-59
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• 2005

SLSV (single loop single vector) method is to solve the excessive computational cost problem in RBDO (reliability-based design optimization) by decoupling the nested iteration loops. However, the practical use of SLSV method to RBDO case is limited by the instability or inaccuracy of the method since it often diverges or converges to a wrong solution. Thus, in this paper, a new modified SLSV method is proposed. This method improves its convergence capability effectively by utilizing Inactive Design and Active MPP Design together with modified HMV (hybrid mean value) method. The usefulness of the proposed method is also verified through numerical examples.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.72-81
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• 2011

In this paper, we proposed and designed a novel floating point converter which supports single and double precisions of IEEE754 standard. The proposed convertor supports conversions between floating point number single/double precision and signed fixed point number(32bits/64bits) as well as conversions between signed integer(32bits/64bits) and floating point number single/double precision and conversions between floating point number single and double precisions. We defined a new internal format to convert various input types into one type so that overflow checking could be conducted easily according to range of output types. The internal format is similar to the extended format of floating point double precision defined in IEEE754 2008 standard. This standard specifies that minimum exponent bit-width of the extended format of floating point double precision is 15bits, but 11bits are enough to implement the proposed converting unit. Also, we optimized rounding stage of the convertor unit so that we could make it possible to operate rounding and represent correct negative numbers using an incrementer instead an adder. We designed single cycle data path and 5 cycles data path. After describing the HDL model for two data paths of the convertor, we synthesized them with TSMC 180nm technology library using Synopsys design compiler. Cell area of synthesis result occupies 12,886 gates(2 input NAND gate), and maximum operating frequency is 411MHz.

• Journal of Power Electronics
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• v.11 no.2
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• pp.218-227
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• 2011

The subject of variable step size maximum power point tracking (MPPT) algorithms has been addressed in the literature. However, most of the addressed algorithms tune the variable step size according to two variables: the photovoltaic (PV) array voltage ($V_{PV}$) and the PV array current ($I_{PV}$). Therefore, both the PV array current and voltage have to be measured. Recently, maximum power point trackers that arc based on a single variable ($I_{PV}$ or $V_{PV}$) have received a great deal of attention due to their simplicity and ease of implementation, when compared to other tracking techniques. In this paper, two methods have been proposed to design a variable step size MPPT algorithm using only a single current sensor for stand-alone battery storage PV systems. These methods utilize only the relationship between the PV array measured current and the converter duty cycle (D) to automatically adapt the step change in the duty cycle to reach the maximum power point (MPP) of the PV array. Detailed analyses and flowcharts of the proposed methods are included. Moreover, a comparison has been made between the proposed methods to investigate their performance in the transient and steady states. Finally, experimental results with field programmable gate arrays (FPGAs) are presented to verify the performance of the proposed methods.