• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 F
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• pp.1925-1927
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• 1998

D-STATCON using the multilevel voltage source inverters is presented for voltage regulation and reactive power compensation in distribution system. This cascade M-level inverter consists of (M-1)/2 single phase full bridge inverter(FBI). This multilevel inverter is a natural fit to the flexible ac transmission systems(FACTS) including STATCON, SVC, series compensation and phase shifting, It can solve the problems of conventional transformer-based multipulse inverters and multilevel diode-clamped inverters. From the simulation results, the superiority of D-STATCON with cascade multilevel inverter is shown for high power application.

• Journal of Power Electronics
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• 제16권5호
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• pp.1706-1715
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• 2016

In this paper, a single phase modified switched-diode topology for both symmetrical and asymmetrical cascaded multilevel inverters is presented. It consists of a Modified Switched-Diode Unit (MSDU) and a Twin Source Two Switch Unit (TSTSU) to produce distinct positive voltage levels according to the operating modes. An additional H-bridge synthesizes a voltage waveform, where the voltage levels of either polarity have less Total Harmonic Distortion (THD). Higher-level inverters can be built by cascading MSDUs. A comparative analysis is done with other topologies. The proposed topology results in reductions in the number of power switches, losses, installation area, voltage stress and converter cost. The Nearest Level Control (NLC) technique is employed to generate the gating signals for the power switches. To verify the performance of the proposed structure, simulation results are carried out by a PSIM under both steady state and dynamic conditions. Experimental results are presented to validate the simulation results.

• 조명전기설비학회논문지
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• 제28권11호
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• pp.68-76
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• 2014

This paper presents an offset error compensation algorithm for the accurate phase angle of the grid voltage in single-phase grid-connected inverters. The offset error generated from the grid voltage measurement process cause the fundamental harmonic component with grid frequency in the synchronous reference frame phase lock loop (PLL). As a result, the grid angle is distorted and the power quality in power systems is degraded. In addition, the dq-axis currents in the synchronous reference frame and phase current have the dc component, first and second order ripples compared with the grid frequency under the distorted grid angle. In this paper, the effects of the offset and scaling errors are analyzed based on the synchronous reference frame PLL. Particularly, the offset error can be estimated from the integrator output of the synchronous reference frame PLL and compensated by using proportional-integral controller. Moreover, the RMS (Root Mean Square) function is proposed to detect the offset error component. The effectiveness of the proposed algorithm is verified through simulation and experiment results.

• Journal of Power Electronics
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• 제15권5호
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• pp.1227-1234
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• 2015

The efficient electric power demand management in electric power supply industry is currently being changed by distributed generation. Meanwhile, small-scale distributed generation systems using renewable energy are being constructed worldwide. Several small-scale renewable distributed generation systems, which can supply electricity to the grid at peak load of the grid as per policy such as demand response programs, could help in the stability of the electric power demand management. In this case, the power quality of the small-scale renewable distributed generation system is more significant. Low prices of power semiconductors and multilevel inverters with high power quality have been recently investigated. However, the conventional multilevel inverter topology is unsuitable for the small-scale renewable distributed generation system, because the number of devices of such topology increases with increasing output voltage level. In this paper, a single-phase multilevel inverter based on H-bridge, with DC_Link divided by bi-directional switches, is proposed. The proposed topology has almost half the number of devices of the conventional multilevel inverter topology when these inverters have the same output voltage level. Double Fourier series solution is mainly used when comparing PWM output harmonic components of various inverter topologies. Harmonic components of the proposed multilevel inverter, which have been analyzed by double Fourier series, are compared with those of the conventional multilevel inverter. An inverter prototype is then developed to verify the validity of the theoretical analysis.

• 조명전기설비학회논문지
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• 제29권10호
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• pp.73-82
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• 2015

This paper proposes an ripple reduction algorithm and analyzes the effects of offset and scale errors generated by voltage sensor while measuring grid voltage in grid-tied single-phase inverters. Generally, the grid-connected inverter needs to detect the phase angle information by measuring grid voltage for synchronization, so that the single-phase inverter can be accurately driven based on estimated phase angle information. However, offset and scale errors are inevitably generated owing to the non-linear characteristics of voltage sensor and these errors affect that the phase angle includes 1st harmonic component under using SRF-PLL(Synchronous Reference Frame - Phase Locked Loop) system for detecting grid phase angle. Also, the performance of the overall system is degraded from the distorted phase angle including the specific harmonic component. As a result, in this paper, offset and scale error due to the voltage sensor in single-phase grid connected inverter under SRF-PLL is analyzed in detail and proportional resonant controller is used to reduce the ripples caused by the offset error. Especially, the integrator output of PI(Proportional Integral) controller in SRF-PLL is selected as an input signal of the proportional resonant controller. Simulation and experiment are performed to verify the effectiveness of the proposed algorithm.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2018년도 추계학술대회
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• pp.95-97
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• 2018

The power quality of Single Phase Grid-Connected Inverters (GCIs) has received much attention with the increasing number of Distributed Generation (DG) systems. However, the performance of single phase GCIs get degraded due to several factors such as the grid voltage harmonics, the dead time effect, and the turn ON/OFF of the switches, which causes the harmonics at the output of GCIs. Therefore, it is not easy to satisfy the harmonic standards such as IEEE 519 and P1547 without the help of harmonic compensator. To meet the harmonic standards a certain kind of harmonic controller needs to be added to the current control loop to effectively mitigate the low order harmonics. In this paper, the harmonic compensation is performed using a novel robust harmonic compensation method based on Digital Lock-in Amplifier (DLA). In the proposed technique, DLAs are used to extract the amplitude and phase information of the harmonics from the output current and compensate it by using a simple PI controller in the feedforward manner. In order to show the superior performance of the proposed harmonic compensation technique, it is compared with those of conventional harmonic compensation methods in terms of the effectiveness of harmonic elimination, complexity, and implementation. The validity of the proposed harmonic compensation techniques for the single phase GCIs is verified through the experimental results with a 5kW single phase GCI. Index Terms -Single Phase Grid Connected Inverter (SPGCI), Harmonic Compensation Method, Total Harmonic Distortion (THD) and Harmonic Standard.

• 전력전자학회논문지
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• 제20권3호
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• pp.201-208
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• 2015

The effects of dead-time and offset error, which cause output current distortion in single-phase grid-connected inverters are investigated this paper. Offset error is typically generated by measuring phase current, including the voltage unbalance of analog devices and non-ideal characteristics in current measurement paths. Dead-time inevitably occurs during generation of the gate signal for controlling power semiconductor switches. Hence, the performance of the grid-connected inverter is significantly degraded because of the current ripples. The current and voltage, including ripple components on the synchronous reference frame and stationary reference frame, are analyzed in detail. An algorithm, which has the proportional resonant controller, is also proposed to reduce current ripple components in the synchronous PI current regulator. As a result, computational complexity of the proposed algorithm is greatly simplified, and the magnitude of the current ripples is significantly decreased. The simulation and experimental results are presented to verify the usefulness of the proposed current ripple reduction algorithm.

• Journal of Power Electronics
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• 제17권5호
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• pp.1338-1348
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• 2017

In this study, a modified ripple correlation control (RCC) maximum-power point-tracking (MPPT) algorithm is proposed for a single-stage single-phase voltage source inverter (VSI) on a grid-connected photovoltaic system (GCPVS). Unlike classic RCC methods, the proposed algorithm does not require high-pass and low-pass filters or the increment of the AC component filter function in the voltage control loop. A simple arithmetic mean function is used to calculate the average value of the photovoltaic (PV) voltage, PV power, and PV voltage ripples for the MPPT of the RCC method. Furthermore, a high-accuracy and high-precision MPPT is achieved. The performance of the proposed algorithm for the single-stage single-phase VSI GCPVS is investigated through simulation and experimental results.

• Journal of Power Electronics
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• 제16권1호
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• pp.18-26
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• 2016

This paper proposes a compensation algorithm for reducing a specific ripple component on synchronous reference frame phase locked loop (SRF-PLL) in grid-tied single-phase inverters. In general, SRF-PLL, which is based on all-pass filter to generate virtual voltage, is widely used to estimate the grid phase angle in a single-phase system. In reality, the estimated grid phase angle might be distorted because the phase difference between actual and virtual voltages is not 90 degrees. That is, the phase error is caused by the difference between cut-off frequency of all-pass filter and grid frequency under grid frequency variation. Therefore, the effects on phase angle and output current attributed to the phase error are mathematically analyzed in this paper. In addition, the proportional resonant (PR) controller is adapted to reduce the effects of phase error. The validity of the proposed algorithm is verified through several simulations and experiments.

• 전력전자학회논문지
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• 제24권6호
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• pp.396-405
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• 2019

Single-phase full-bridge inverters have shoot-through problems. Dead time is an essential way of solving these issues, but it distorts the output voltage and current. Dual-buck inverters are designed to eliminate the abovementioned problems. However, these inverters result in switching power loss and electromagnetic interference due to the diode reverse-recovery problem. Previous studies have suggested reducing the switching power loss from diode reverse-recovery, but their proposed methods have complex circuit configurations and high system costs. To alleviate the switching power loss from diode reverse-recovery, the current work proposes a dual-buck inverter with a coupled inductor. In the structure of the proposed inverter, the current flowing into the original diode is divided into a new diode. Therefore, the switching power loss is reduced, and the efficiency of the proposed inverter is improved. Simulation waveforms and experimental results for a 1.0 kW prototype inverter are discussed to verify the performance of the proposed inverter.