• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.8 s.111
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• pp.732-738
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• 2006

Divide-by-2 and divide-by-4 circuits which can operate up to 10 GHz are designed. A design method used in these circuits is the TSPC(True Single Phase Clocking) topology. The structure of the TSPC dividers is very simple because they need only a single clock and purely consist of smalt sized cmos devices. Through measurements, we find the fact that in proportion to the bias voltage, the free running frequency increases and the operation region also moves toward a higher frequency region. For operating conditions of bias voltage $3.0{\sim}4.0V$, input power 16dBm and dcoffset $1.5{\sim}2.0V$, 5 GHz and 2.5 GHz output signals divided by 2 and 4 are measured. The layout size of the divide-by-2 circuit is about $500{\times}500 um^2$($50{\times}40um^2$ except pad interconnection part).

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.2
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• pp.56-61
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• 2010

In this paper, high efficient power amplifier with dual band has been realized. Dual band power amplifier have used modify stub matching for single FET, center frequency 2.14GHz and 5.2GHz respectively. The dual-band operation of the CRLH TL is achieved by the frequency offset and the nonlinear phase slope of the CRLH TL for the matching network of the power amplifier. Because the control of the all harmonic components is very difficult m dual-band, we have managed only the second- and third-harmonics to obtain the high efficiency with the CRLH TL in dual-band. Dual-band characteristics in the output has to balance. Two operating frequencies are chosen at 2.14 GHz and 5.2 GHz in this work. The measured results show that the output power of 28.56 dBm and 29 dBm was obtained at 2.14 GHz and 5.2 GHz, respectively. At this point, we have obtained the power-added efficiency (PAE) of 65.824 % and 69.86 % at two operation frequencies, respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.12
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• pp.3587-3593
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• 2009

Nowadays, the PV systems have been focused on the interconnection between the power source and the grid. The PV inverter, either single-phase or three-phase, can be considered as the core of the whole system because of an important role in the grid-interconnecting operation. An important issue in the inverter control is the load current regulation. In the literature, the Proportional+Integral (PI) controller, normally used in the current-controlled Voltage Source Inverter (VSI), cannot be a satisfactory controller for an ac system because of the steady-sate error and the poor disturbance rejection, especially in high-frequency range. By comparison with the PI controller, the Proportional+Resonant (PR) controller can introduce an infinite gain at the fundamental ac frequency; hence can achieve the zero steady-state error without requiring the complex transformation and the dq-coupling technique. In this paper, a PR controller is designed and adopted for replacing the PI controller. Based on the theoretical analyses, the PR controller based control strategy is implemented in a 32-bit fixed-point TMS320F2812 DSP and evaluated in a 3kW experimental prototype Photovoltaic (PV) power conditioning system (PCS). Simulation and experimental results are shown to verify the performance of implemented control scheme in PV PCS.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.3
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• pp.258-265
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• 2011

This paper presents a variable frequency current control scheme for the air-pressure control of diaphragm. Differ from the conventional air-pressure control of diaphragm, the proposed method uses a single-phase inverter to control the phase current and frequency. The phase current is adjusted to keep the reference air-pressure of the diaphragm. And the current frequency is changed to reduce the mechanical vibration. In order to smooth change of the operation with a constant air-pressure, the frequency is changed according to the voltage reference from the current controller. When the phase current is satisfied to the constant air-pressure, the current frequency is increased to reduce the vibration of the diaphragm. When the reference voltage to keep the phase current is over than the set value, the current frequency is decreased to keep the air-pressure. The proposed control scheme is verified by the experimental test of a commercial diaphragm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.3
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• pp.401-417
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• 1994

In this paper, a new testable design technique for domino CMOS circuits is proposed to detect stuck-at(s-at), stuck-open(s-op) and stuck-on(s-on) faults in the circuits by observing logic test reponses. The proposed technique adds one pMOS transistor per domino CMOS gate for s-op and s-on faults testing of nMOS transistors and one nMOS transistors and one nMOS transistor per domino gate or multilevel circuit to detect s-on faults in pMOS transistors of inverters in the circuit. The extra transistors enable the proposed testable circuit to operate like a pseudo static nMOS circuit while testing nMOS transistors in domino CMOS circuits. Therefore, the two=phase operation of a precharge phase and a evaluation phase is not needed to keep the domino CMOS circuit from malfunctionong due to circuit delays in the test mode, which reduces the testing time and the complexity of test generation. Most faults of th transistors in the proposed testable domino CMOS circuit can be detected by single test patterns. The use of single test patterns makes the testing of the proposed testable domino CMOS circuit free from path delays, timing skews, chage sharing and glitches. In the proposed design, the testing of the faults which, require test sequences also becomes free from test invalidation. The conventional automatic test pattern generators(ATPG) can be used for generating test patterns to detect faults in the circuits.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2003.10a
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• pp.24-29
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• 2003

Deep sea water has cold temperature, abundant nutrients and minerals, and good water quality that is pathogen-free and stable. Compared with surface water, deep sea water contains more nutrition salt, such as nitrogen and phosphor. Moreover, if has the good balance of minerals. Because of the ability of the spray drying process to produce a free-flowing power considering of spherical particles with a well-defined size distribution and the rapid drying times for heat-sensitive material, spray drying is attractive for a wide range of applications spray drying is a unique unit operation in which powders are produced from a liquid feed in a single processing step. Key component of the process are atomizer, spray chamber. Design of spray chamber should be based on the atomizer type, the production rate, and the particle size required. Because of the complex processes taking place during spray drying, traditional design method are based on pilot-plant tests and empirical scale-up rules. Modern technique such as CFD have a role to play in design and troubleshooting.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.267-273
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• 2007

A fractional-N frequency synthesizer supports quadruple bands and multiple standards for mobile broadcasting systems. A novel linearized coarse tuned VCO adopting a pseudo-exponential capacitor bank structure is proposed to cover the wide bandwidth of 65%. The proposed technique successfully reduces the variations of KVCO and per-code frequency step by 3.2 and 2.7 times, respectively. For the divider and prescaler circuits, TSPC (true single-phase clock) logic is extensively utilized for high speed operation, low power consumption, and small silicon area. Implemented in $0.18-{\mu}m$ CMOS, the PLL covers $154{\sim}303$ MHz (VHF-III), $462{\sim}911$ MHz (UHF), and $1441{\sim}1887$ MHz (L1, L2) with two VCO's while dissipating 23 mA from 1.8 V supply. The integrated phase noise is 0.598 and 0.812 degree for the integer-N and fractional-N modes, respectively, at 750 MHz output frequency. The in-band noise at 10 kHz offset is -96 dBc/Hz for the integer-N mode and degraded only by 3 dB for the fractional-N mode.

• International Journal of Fluid Machinery and Systems
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• v.2 no.4
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• pp.315-323
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• 2009

Pressure oscillations triggered by the unstable interaction of dynamic flow features of the hydraulic turbine with the hydraulic plant system - including the electrical design - can at times reach significant levels and could lead to damage of plant components or could reduce component lifetime significantly. Such a problem can arise for overload as well as for part load operation of the turbine. This paper discusses an approach to analyze the overload high pressure oscillation problem using computational fluid dynamic (CFD) modeling of the hydraulic machine combined with a network modeling technique of the hydraulic system. The key factor in this analysis is the determination of the overload vortex rope volume occurring within the turbine under the runner which is acting as an active element in the system. Two different modeling techniques to compute the flow field downstream of the runner will be presented in this paper. As a first approach, single phase flow simulations are used to evaluate the vortex rope volume before moving to more sophisticated modeling which incorporates two phase flow calculations employing cavitation modeling. The influence of these different modeling strategies on the simulated plant behavior will be discussed.

• Proceedings of the KIEE Conference
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• 2001.07a
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• pp.134-136
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• 2001

This paper describes the application of Fuzzy Power System Stabilizer(FPSS) for improving dynamic stability of power system. The Real-coding Genetic Algorithm(RGA) was applied to optimize gains of the inputs and outputs of the FPSS. The effectiveness of the proposed FPSS was demonstrated by simulation studies for single-machine infinite system. To show the superiority of the proposed FPSS, its performances were compared with those of Conventional Power System Stabilizer(CPSS) The proposed FPSS showed better control performances than the CPSS in three-phase ground fault under a normal load which was system condition in tuning FPSS. To show the robustness of the proposed FPSS, it was applied to damp the low frequency oscillations caused by disturbances such as three-phase ground fault under heavy and light load conditions. The proposed FPSS showed better performance than CPSS in terms of the settling time and damping effect for power system operation condition.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2099-2108
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• 2016

The cascaded multilevel converter is widely adopted to medium/high voltage and high power electronic applications due to the small harmonic components of the output voltage and the facilitation of modularity. In this paper, the operation principle of a T-type H-bridge topology is investigated in detail, and a carrier phase shifted pulse width modulation (CPS-PWM) based control method is proposed for this topology. Taking a virtual five-level waveform achieved by a unipolar double frequency CPS-PWM as the output object, PWM signals of the T-type H-bridge can be obtained by reverse derivation according to its switching modes. In addition, a control method for the T-type H-bridge based cascaded multilevel converter is introduced. Then a single-phase T-type H-bridge cascaded multilevel static var generator (SVG) prototype is built, and a repetitive controller based compound current control strategy is designed with the DC-link voltage balancing control scheme analyzed. Finally, simulation and experimental results validate the correctness and feasibility of the proposed modulation method and control strategy for T-type H-bridge based cascaded multilevel converters.