• Proceedings of the KIPE Conference
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• 1998.07a
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• pp.31-34
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• 1998

In this paper, a Single-phase Active Rectifier(SAR) with high power factor capability for inverter air-conditioner is adopted for satisfying the international standards of input current harmonics, IEC 1000-3-2. Comparing the conventional boost power factor correction circuit, one diode drop is reduced in the power flow path of the SAR circuit, so the system efficiency is improved. To apply the control IC, such as UC3854, ML4821 and so forth, to the SAR, the adequate sensing circuits are proposed. The design rules of passive components and two control loops are also presented. The prototype SAR circuit with 3㎾ power consumption is builted and tested to verify the operation of the proposed circuit.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.375-378
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• 2002

This paper describes tile design and implementation of contact and contactless If card OS(Operating System) for Java Card, namely JCOS(Java Card 05). The JCOS complies with ISO/IEC 7816 and IS0/1EC 14443 standards. The JCOS conforms to Java Card 2.1.2 specifications. The JCOS is running on 32-bit ARMTTDMI with public key crypto-coprocssor. This paper describes only the dual-interface protocol of the JCOS which supports contact and contactless applications in a single chip. The JCOS has been completed with our sample banking service and access control service in ETRI up to now.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.493-496
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• 2003

This paper studied the method to improve the reliability with the simple structure and the decreased calculation of Micro-Controller(uC) in Power Line Modem. We have implementation the program which correct the 1-bit error of the $\mu$C within the control system and the DS/SS(Direct sequence/spread spectrum) by adding the simple circuit between a single chip powerline transceiver IC and a uC.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.2
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• pp.228-233
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• 2000

It is common to apply the technology of FPGA (Fie이 Programmable Gate Array) which is one of the design methods for ASIC(Application Specific IC)to the active components used in the data processing at the digital system of satellite aircraft missile etc for compact lightness and integration of Printed Circuit Board (PCB) In carrying out the digital data processing the FPGAs are designed for the various functions of the Process Control Interrupt Control Clock Generation Error Detection and Correction (EDAC) as the individual module. In this paper an FPGA chip for Single Error Correction and Double Error Detection (SEC-DED) for EDAC is designed and simulated by using a VLSI design software LODECAP.

• Molecular & Cellular Toxicology
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• v.1 no.4
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• pp.230-236
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• 2005

Formaldehyde is a common environmental contaminant found in tobacco smoke, paint, garments, diesel and exhaust, and medical and industrial products. Formaldehyde has been considered to be potentially carcinogenic, making it a subject of major environmental concern. However, only a little information on the mechanism of immunological sensitization and asthma by this compound has been known. So, we performed with Jurkat cell line, a human T lymphocyte, to assess the induction of DNA damage and to identify the DEGs related to immune response or toxicity by formaldehyde. In this study, we investigated the induction of DNA single strand breaks by formaldehyde using single cell gel electrophoresis assay (comet assay). And we compared gene expression between control and formaldehyde treatment to identify genes that are specifically or predominantly expressed by employing annealing control primer (ACP)-based $GeneFishing^{TM}$ method. The cytotoxicity ($IC_{30}$) of formaldehyde was determined above the 0.65 mM in Jurkat cell in 48 h treatment. Based on the $IC_{30}$ value from cytotoxicity test, we performed the comet assay in this concentration. From these results, 0.65 mM of formaldehyde was not revealed significant DNA damages in the absence of S-9 metabolic activation system. And the one differentially expressed gene (DEG) of formaldehyde was identified to zinc finger protein 292 using $GeneFishing^{TM}$ method. Through further investigation, we will identify more meaningful and useful DEGs on formaldehyde, and then can get the information on the associated mechanism and pathway with immune response or other toxicity by formaldehyde exposure.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.2
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• pp.80-86
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• 2011

This paper presents an integrated variable amplitude high voltage pulse generation circuit with low power and small size for driving industrial piezoelectric printer heads. To solve the problems of large size and power overhead of conventional pulse generators that usually assembled with multiple high-cost discrete ICs on a PCB board, we have designed a new integrated circuit (IC) chip. Since all the functions are integrated on to a single-chip it can achieve low cost and control the high-voltage output pulse with variable amplitudes as well. It can also digitally control the rising and falling times of an output high voltage pulse by using programmable RC time control of the output buffer. The proposed circuit has been designed and simulatedd in a 180[nm] Bipolar-CMOS-DMOS (BCD) technology using HSPICE and Cadence Virtuoso Tools. The proposed single-chip pulse generation circuit is suitable for use in industrial printer heads requiring a variable high voltage driving capability.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.1
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• pp.70-77
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• 2008

Conventional PDP power system, which commonly uses two isolation transformer, consists of sustaining power ($V_S$), addressing power($V_A$), and Multi power($V_M$). Because each of these power conversion circuits use transformer and control IC, there are several defects: decrease of efficiency, rise of cost, and parts stress. This paper is proposed the method which operates PDP power system only with one transformer. The proposed method contributes not only to high-efficient performance of the DC/DC power stage and improvement of reliability but also to reduction of cost by reducing volume and size. Also, proposed method is proper to Address Display-period Separation(ADS) which is one of the driving methods of PDP. Superiority of the proposed method is proved by comparison with conventional method and theoretical, experimental analysis.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.155-164
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• 1996

The architecture of a programmable video codec IC is described that employs multiple vector processors in a single chip. The vector processors operate in parallel and communicate with one another through on-chip shared memories. A single scalar control processor schedules each vector processor independently to achieve real-tiem video coding with special vector instructions. With programmable interconnection buses, the proposed architecture performs multi-processing of tasks and data in video coding. Therefore, it can provide good parallelism as well as good programmability. especially, it can operate multithread video coding, which processes several independent image sequences simultaneously. We explain its scheduling, multithred video coding, and vector processor architectures. We implemented a prototype video codec with a 0.8um CMOS cell-based technology for the multi-standard videophone. This codec can execute video encoding and decoding simultaneously for the QCIF image at a frame rate of 30Hz.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.677-682
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• 1998

A Single-phase Active Rectifier (SAR) [4-6] with high power factor capability is adopted to satisfy the international harmonic current standards such as IEC 1000-3-2. To minimize the input current distortion and to apply the control IC, such as FA5331, UC3854, ML4821 and so forth, the new adequate sensing circuits of the input voltage and current are proposed. There are tow methods applicable the SAR to inverter air-conditioner from the viewpoint of both efficiency and cost. The selecting methods of the passive components are presented for the two approaches. Using the determined components, the loss analyses are carried out. The prototype SAR circuits of these two approaches with 3kW power consumption are built and the operation and performance of the circuits with power factor correction capability are verified through the experimental results.

• Progress in Superconductivity and Cryogenics
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• v.10 no.1
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• pp.6-9
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• 2008

We have investigated the MOD process successfully for the fabrication of the YBCO thick film on the $LaAlO_3$(001) single crystalline substrate. The cracking problem in YBCO thick film, a serious problem in the conventional TFA-MOD method, could be overcome with a careful control of precursor materials. Thus coating solution was prepared for the YBCO thick film by using fluorine-free precursor material. The precursor solutions were coated on the LAO(001) single crystalline substrate using the dip coating method, calcined at the temperature up to $500^{\circ}C$, and fired at various high temperatures for 2 h in a reduced oxygen atmosphere. Optimally processed YBCO thick film exhibited high critical current($I_c$) over 200 A/cm-width at 77K in self-field.