• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.11a
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• pp.33-36
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• 1999

In this paper, we proposed a simultaneous switching noise(SSN) reduction technique in muti-layer beards(MLB) for high-speed digital applications and analyzed them using the Finite Difference Time Domain(FDTD) method. The new method by conductive dielectric substrates reduces SSN couplings and resonances, significantly, which cause series malfunctions in the modem high-speed digital applications.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.4
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• pp.9-14
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• 1999

In this paper, we proposed a simultaneous switching noise (SSN) reduction technique in multi-layer boards (MLB) for high-speed digital applications and analyzed it using the Finite Difference Time Domain (FDTD) method. The new structure using conductive dielectric substrates is effective for the reduction of SSN couplings and resonances. The uniform insertion of the conducive layer reduced the SSN coupling and resonance by 85% and the partial insertion only around the edges reduced by 55% respectively.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.389-392
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• 1999

It is essential to estimate an effective inductance in a ground plane of muliti-layer IC package system in order to determine the simultaneous switching noise of the package. A new method to estimate the effective ground inductance in multi-layer IC package is presented. With the estimated ground plane inductance values, maximum switching noise variations according to the number of simultaneously switching drivers are investigated by developing a new SSN model. These results are verified by performing HSPICE simulation with the 0.35${\mu}{\textrm}{m}$ CMOS technology.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.3
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• pp.115-119
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• 2001

This paper presents an efficient and simple method for analyzine maximum simultaneous switching noise (SSN) on ground interconnection networks in CMOS systems. For the derivation of maximum SSN expression, we use ${\alpha}$-power law MOS model and Taylor's series approximation. The accuracy of the proposed method is verified by comparing the results with those of previous researches and HSPICE simulations under the contemporary process parameters and environmental conditions. The proposed method predicts the maximum SSN values more accurately when compared to existing approaches even in most practical cases such that exist some output drivers not in transition.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.44-50
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• 2002

A novel technique for minimization of simultaneous switching noise is Presented. Dual Layer Power Line (DLPL) structure i:; newly proposed for a possible silicon realization of a mutual inductor, with which an instant large current in the power line is half-divided flowing through two different, but closely coupled, layers in opposite directions. This mutual inductance between two power layers enables us to significantly reduce the switching noise. SPICE simulations show that with a mutual coupling coefficient higher than 0.8, the switching noise reduces by 63% compared to the previously reported solutions. This DLPL technique can also be applied to PCB artworks.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.55-63
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• 1999

A new CMOS If Package design methodology is presented, analyzing the electrical characteristics of a package and its effects on the CMOS digital circuits. An analytical investigation of the package noise effects due to the simultaneous switching of the gates within a chip, i.e., simultaneous switching noise (SSN) is performed. Then not only are novel design formula to meet electrical constraints of the Package derived, but also package design methodology based on the formula is proposed. Further, in order to demonstrate the Proposed design methodology, the design results are compared with HSPICE (a general purpose circuit simulator) simulation for $0.3\mu\textrm{m}$-based CMOS circuits. According to the proposed design procedures, it is shown that the results have excellent agreements with those of HSPICE simulation.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.97-101
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• 2013

There is a growing need for optical communication systems that convert large volumes of data to optical signals and that accommodate and transmit the signals across long distances. Digital optical communication consists of a master unit (MU) and a slave unit (SU). The MU transmits data to SU using digital optical signals. However, digital optical units that are commercially available or are under development transmit data using two's complement representation. At low input levels, a large number of SSOs (simultaneous switching outputs) are required because of the high rate of bit switching in two's complement, which thereby increases the power noise. This problem reduces the overall system capability because a DSP (digital signal processor) chip (FPGA, CPLD, etc.) cannot be used efficiently and power noise increases. This paper proposes a change from two's complement to a more efficient method that produces less SSO noise and can be applied to existing digital optical units.

• ETRI Journal
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• v.32 no.2
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• pp.265-272
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• 2010

To supply a power distribution network with stable power in a high-speed mixed mode system, simultaneous switching noise caused at the multilayer PCB and package structures needs to be sufficiently suppressed. The uni-planar compact electromagnetic bandgap (UC-EBG) structure is well known as a promising solution to suppress the power noise and isolate noise-sensitive analog/RF circuits from a noisy digital circuit. However, a typical UC-EBG structure has several severe problems, such as a limitation in the stop band's lower cutoff frequency and signal quality degradation. To make up for the defects of a conventional EBG structure, a partially located EBG structure with decoupling capacitors is proposed in this paper as a means of both suppressing the power noise propagation and minimizing the effects of the perforated reference plane on the signal quality. The proposed structure is validated and investigated through simulation and measurement in both frequency and time domains.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1141-1144
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• 1998

A new design methodology for the shortchannel CMOS IC-package is presented. It is developed by representing the package inductance with an effective lumpedinductance. The worst case maximum-simultaneous-switching noise (SSN) and gate propagation delay due to the package are modeled in terms of driver geometry, the maximum number of simultaneous switching drivers, and the effective inductance. The SSN variations according to load capacitances are investigated with this model. The package design techniques based on the proposed guidelines are verified by performing HSPICE simulations with the $0.35\mu\textrm{m}$ CMOS model parameters.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.129-132
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• 2001

This paper presents an efficient method to estimate the maximum SSN (simultaneous switching noise) for ground interconnection networks in CMOS systems using Taylor's series and analyzes the truncation error that has occurred in Taylor's series approximation. We assume that the curve form of noise voltage on ground interconnection networks is linear and derive a polynomial expression to estimate the maximum value of SSN using $\alpha$-power MOS model. The maximum relative error due to the truncation is shown to be under 1.87% through simulations when we approximate the noise expression in the 3rd-order polynomial.