• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.49-60
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• 2010

Semiconductor packages are increasingly moving toward miniaturization, lighter and high performance. Futhermore, packages become thinner. Thin packages will generate serious reliability problems such as warpage, crack and other failures. Reliability problems are mainly caused by the CTE mismatch of various package materials. Therefore, proper selection of the package materials and geometrical optimization is very important for controlling the warpage and the stress of the package. In this study, we investigated the characteristics of the warpage and the stress of several packages currently used in mobile devices such as CABGA, fcSCP, SCSP, and MCP. Warpage and stress distribution are analyzed by the finite element simulation. Key material properties which affect the warpage of package are investigated such as the elastic moduli, CTEs of EMC molding and the substrate. Geometrical effects are also investigated including the thickness or size of EMC molding, silicon die and substrate. The simulation results indicate that the most influential factors on warpage are EMC molding thickness, CTE of EMC, elastic modulus of the substrate. Simulation results show that warpage is the largest for SCSP. In order to reduce the warpage, DOE optimization is performed, and the optimization results show that warpage of SCSP becomes $10{\mu}m$.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.1
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• pp.31-39
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• 2014

For mobile application, semiconductor packages are increasingly moving toward high density, miniaturization, lighter and multi-functions. Typical wafer level packages (WLP) is fan-in design, it can not meet high I/O requirement. The fan-out wafer level packages (FOWLPs) with reconfiguration technology have recently emerged as a new WLP technology. In FOWLP, warpage is one of the most critical issues since the thickness of FOWLP is thinner than traditional IC package and warpage of WLP is much larger than the die level package. Warpage affects the throughput and yield of the next manufacturing process as well as wafer handling and fabrication processability. In this study, we investigated the characteristics of warpage and main parameters which affect the warpage deformation of FOWLP using the finite element numerical simulation. In order to minimize the warpage, the characteristics of warpage for various epoxy mold compounds (EMCs) and carrier materials are investigated, and DOE optimization is also performed. In particular, warpage after EMC molding and after carrier detachment process were analyzed respectively. The simulation results indicate that the most influential factor on warpage is CTE of EMC after molding process. EMC material of low CTE and high Tg (glass transition temperature) will reduce the warpage. For carrier material, Alloy42 shows the lowest warpage. Therefore, considering the cost, oxidation and thermal conductivity, Alloy42 or SUS304 is recommend for a carrier material.

• The Bulletin of The Korean Astronomical Society
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• v.46 no.2
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• pp.53.3-53.3
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• 2021

Adaptive Optics (AO) was first studied in the field of astronomy, and its applications have been extended to the field of laser, microscopy, bio, medical, and free space laser communication. AO modelling and simulation are required throughout the system development process. It is necessary not only for proper design but also for performance verification after the final system is built. In KASI, we are trying to develop the AO Python Package for AO modelling and simulation. It includes modelling classes of atmosphere, telescope, Shack-Hartmann wavefront sensor, deformable mirror, which are the components for an AO system. It also includes the ability to simulate the entire AO system over time. It is being developed in the Super Eye Bridge project to develop a segmented mirror, an adaptive optics, and an emersion grating spectrograph, which are future telescope technologies. And it is planned to be used as a performance analysis system for several telescope projects in Korea.

• Proceedings of the Korea Society for Simulation Conference
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• 2001.05a
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• pp.36-42
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• 2001

This paper presents the operational planning systems of automated container terminals. The proposed system is composed of berth allocation module, yard planning module, resource allocation module, sequencing module, and simulation module. All the sub-modules except resource allocation module are built into integrated simulation model using simulation package AutoMod. Simulation experiments are performed according to the number of AGVs and AGV allocation policies.

• Journal of the Semiconductor & Display Technology
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• v.17 no.4
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• pp.42-45
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• 2018

As The semiconductor decrease from 10 nanometer to 7 nanometer, It is suggested that "More than Moore" is needed to follow Moore's Law, which has been a guide for the semiconductor industry. Fan-Out Wafer Level Package(FOWLP) is considered as the key to "More than Moore" to lead the next generation in semiconductors, and the reasons are as follows. the fan-out WLP does not require a substrate, unlike conventional wire bonding and flip-chip bonding packages. As a result, the thickness of the package reduces, and the interconnection becomes shorter. It is easy to increase the number of I / Os and apply it to the multi-layered 3D package. However, FOWLP has many issues that need to be resolved in order for mass production to become feasible. One of the most critical problem is the warpage problem in a process. Due to the nature of the FOWLP structure, the RDL is wired to multiple layers. The warpage problem arises when a new RDL layer is created. It occurs because the solder ball reflow process is exposed to high temperatures for long periods of time, which may cause cracks inside the package. For this reason, we have studied warpage in the FOWLP structure using commercial simulation software through the implementation of the reflow process. Simulation was performed to reproduce the experiment of products of molding compound company. Young's modulus and poisson's ratio were found to be influenced by the order of influence of the factors affecting the distortion. We confirmed that the lower young's modulus and poisson's ratio, the lower warpage.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.18-28
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• 1999

A new equivalent circuit model of package (SOP, Small Outline Package) is presented for designing radio frequency integrated circuits (RFIC). In the RF region, the paddle of a package does not work as an ideal ground. Further parasitics due to both coupling and loss have a substantial effect on MMIC. The equivalent circuit model and parameter extraction methodology for the electrical characteristics of the package are described by illustrating the SOP type packages. The accuracy of the model is evaluated by comparing the s-parameters of the commercial full-wave solver and those of HSPICE simulation with the circuit model. The proposed model shows an excellent agreement with full-wave analysis up to about 8GHz.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.109-119
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• 2003

o In order to start SIP Project .Marketing (& ASIC team) should present biz planning, schedule, device/SIP specs., in SIP TFT prior to request SIP development for package development project. .In order to prevent (PCB) revision, test, burn-in, & quality strategy should be fixed by SIP TFT (PE/Test, QA) prior to request for PKG development. .Target product price/cost, package/ test cost should be delivered and reviewed. o Minimum Information for PCB Design, Package Size, and Cost .(Required) package form factor: size, height, type (BGA, QFP), Pin count/pitch .(Estimated) each die size including scribe lane .(Estimated) pad inform. : count, pitch, configuration(in-line/staggered), (open) size .(Estimated) each device (I/O & Core) power (especially for DRAM embedded SIP) .SIP Block diagram, and net-list using excel sheet format o Why is the initial evaluation important\ulcorner .The higher logic power resulted in spec. over of DRAM Tjmax. This caused business drop longrightarrow Thermal simulation of some SIP product is essential in the beginning stage of SIP business planning (or design) stage. (i.e., DRAM embedded SIP) .When SIP is developed using discrete packages, the I/O driver Capa. of each device may be so high for SIP. Since I/O driver capa. was optimized to discrete package and set board environment, this resulted in severe noise problem in SIP. longrightarrow In this case, the electrical performance of product (including PKG) should have been considered (simulated) in the beginning stage of business planning (or design).

• Journal of the Korea Society for Simulation
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• v.19 no.1
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• pp.1-11
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• 2010

K company produces semiconductor package products under the make-to-order policy to supply for domestic and foreign semiconductor manufacturing companies. Its production process is a machine-paced assembly line type, which consists of die sawing, assembly, and test. This paper suggests three plans to increase process throughput based on the process analysis of K company and evaluates them via a simulation model using a real data collected. The three plans are line balancing by adding machines to the bottleneck process, product group scheduling, and reallocation of the operators in non-bottleneck processes. The evaluation result shows the highest daily throughput increase of 17.3% with an effect of 2.8% reduction of due date violation when the three plans are applied together. Payback period for the mixed application of the three plans is obtained as 1.37 years.

• Transactions of the Korean Society of Automotive Engineers
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• v.18 no.5
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• pp.56-61
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• 2010

This paper presents dynamic clearance verification considering engine movement for vehicle engine room package and validates through physical vehicle test. Traditionally, static clearance guide has been used for engine room package, but it's only 2-dimension criteria that results in requiring unnecessary space and it's not possible to conduct engine movement with real driving conditions. Thus, the dynamic DMU considers engine movement based on 28 load cases that are Roll Data analyzed by CAE for maximum engine movement and visualizes part-to-part dynamic clearance into virtual space. The dynamic DMU enables to develop compact engine room package without unnecessary space. The result of comparison between simulation and physical test has 0.892 correlation coefficient.

• Transactions of Materials Processing
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• v.19 no.8
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• pp.474-479
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• 2010

Newly suggested hybrid LED package can reduce the number of LED processes and enhance light efficacy in virtue of its integrated optical patterns. Square-type pyramid pattern was chosen for the integrated optical pattern in this study, and it was proved that the pattern enhances illuminance about three times and luminance about two and half times by optical simulation. Square-type pyramid patterns of 0.02mm height and 0.04mm pitch were successively machined on a copper mold which is necessary for imprinting the integrated pattern. Hybrid LED package with integrated optical pattern will be manufactured with ultra-fine machined mold in future study.