• 전기전자학회논문지
• /
• 제20권2호
• /
• pp.163-166
• /
• 2016

It is important to operate the driving circuit under the optimal condition through precisely sensing the power consumption causing the temperature made mainly by the MOSFET (metal-oxide semiconductor field-effect transistor) when a BLDC (Brushless Direct Current) motor operates. In this letter, a Super-junction (SJ) power TMOSFET (trench metal-oxide semiconductor field-effect transistor) with an ultra-low specific on-resistance of $0.96m{\Omega}{\cdot}cm^2$ under the same break down voltage of 100 V is designed by using of the SILVACO TCAD 2D device simulator, Atlas, while the specific on-resistance of the traditional power MOSFET has tens of $m{\Omega}{\cdot}cm^2$, which makes the higher power consumption. The SPICE simulation for measuring the power distribution of 25 cells for a chip is carried out, in which a unit cell is a SJ Power TMOSFET with resistor arrays. In addition, the power consumption for each unit cell of SJ Power TMOSFET, considering the number, pattern and position of bonding, is computed and the power distribution for an ANSYS model is obtained, and the SJ Power TMOSFET is designed to make the power of the chip distributed uniformly to guarantee it's reliability.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2011년도 제42회 하계학술대회
• /
• pp.1380-1381
• /
• 2011

본 논문에서는 SILVACO 사의 ATHENA와 ATLAS를 이용하여 후면 전극 실리콘 태양전지 (back contact silicon solar cell)의 전면 텍스쳐링 (texturing) 깊이 (depth)와 텍스쳐링 간격 (gap)에 따른 태양전지 효율(efficiency)에 미치는 영향을 분석하였다. 제안한 후면 전극 실리콘 태양전지는 (100) silicon wafer(n-type, $6{\times}10^{15}\;cm^{-3}$)을 기반으로 전면부에 텍스쳐링을, 후면부에 BSF(back surface field, $1{\times}10^{20}\;cm^{-3}$)와 에미터(emitter, $8.5{\times}10^{19}\;cm^{-3}$)를 구성하고, 셀간 피치를 1250 ${\mu}m$, BSF와 에미터의 간격을 25 ${\mu}m$으로 한 구조이다. 텍스쳐링 간격이 없이 텍스쳐링 깊이를 0 ${\mu}m$에서 150 ${\mu}m$으로 증가시켜 분석한 결과, 텍스쳐링 깊이가 증가할수록 효율이 23.90%에서 25.79%로 증가하였다. 텍스쳐링 간격을 1 ${\mu}m$에서 100 ${\mu}m$으로 증가시켜 분석한 결과, 텍스쳐링 깊이와 상관없이 텍스쳐링 간격이 증가할수록 후면 전극 실리콘 태양전지의 효율이 감소하였다. 텍스쳐링 유무에 따라 후면 전극 태양전지의 외부양자효율의 차이를 보였고 텍스쳐링이 있을 때 외부양자효율이 보다 높은 값을 얻었다.

• 한국전기전자재료학회논문지
• /
• 제23권6호
• /
• pp.436-439
• /
• 2010

SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics. In this work, we report the effect of the interface states ($Q_f$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized by using a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. When the $SiO_2$/SiC interface charge decreases, power losses and switching time also decrease, primarily due to the lowered channel mobilities. High density interface states can result in increased carrier trapping, or more recombination centers or scattering sites. Therefore, the quality of $SiO_2$/SiC interfaces has a important effect on both the static and transient properties of SiC MOSFET devices.

• 한국전기전자재료학회논문지
• /
• 제23권10호
• /
• pp.767-770
• /
• 2010

In this work, we investigated the static characteristics of 4H-SiC vertical metal-oxidesemiconductor field effect transistors (VMOSFETs) by adjusting the doping level of n-epilayer and the effect of a current spreading layer (CSL), which was inserted below the p-base region with highly doped n+ state ($5{\times}10^{17}cm^{-3}$). The structure of SiC VMOSFET was designed by using a 2-dimensional device simulator (ATLAS, Silvaco Inc.). By varying the n-epilayer doping concentration from $1{\times}10^{16}cm^{-3}$ to $1{\times}10^{17}cm^{-3}$, we investigated the static characteristics of SiC VMOSFETs such as blocking voltages and on-resistances. We found that CSL helps distribute the electron flow more uniformly, minimizing current crowding at the top of the drift region and reducing the drift layer resistance. For that reason, silicon carbide VMOSFET structures of highly intensified blocking voltages with good figures of merit can be achieved by adjusting CSL and doping level of n-epilayer.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2010년도 하계학술대회 논문집
• /
• pp.350-350
• /
• 2010

Silicon carbide (SiC), one of the well known wide band gap semiconductors, shows high thermal conductivities, chemical inertness and breakdown energies. The design of normally-off 4H-SiC VJFETs [1] has been reported and 4H-SiC VJFETs with different lateral JFET channel opening dimensions have been studied [2]. In this work, 4H-SiC based VJFETs has been designed using the device simulator (ATLAS, Silvaco Data System, Inc). We varied the n-epi layer thickness (from $6\;{\mu}m$ to $10\;{\mu}m$) and the channel width (from $0.9\;{\mu}m$ to $1.2\;{\mu}m$), and investigated the static characteristics as blocking voltages, threshold voltages, on-resistances. We have shown that silicon carbide JFET structures of highly intensified blocking voltages with optimized figures of merit can thus be achieved by adjusting the epi layer thickness and channel width.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
• /
• pp.82-82
• /
• 2008

One-dimensional (1D) nanowires have been received much attention due to their potential for applications in various field. Recently some logic applications fabricated on various nanowires, such as ZnO, CdS, Si, are reported. These logic circuits, which consist of two- or three field effect transistors(FETs), are basic components of computation machine such as central process unit (CPU). FETs fabricated on nanowire generally have surrounded shapes of gate structure, which improve the device performance. Highly integrated circuits can also be achieved by fabricating on nano-scaled nanowires. But the numerical and SPICE simulation about the logic circuitry have never been reported and analyses of detailed parameters related to performance, such as channel doping, gate shapes, souce/drain contact and etc., were strongly needed. In our study, NAND and NOT logic circuits were simulated and characterized using 2- and 3-dimensional numerical simulation (SILVACO ATLAS) and built-in spice module(mixed mode).

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
• /
• pp.83-83
• /
• 2008

Metal-oxide-silicon-on-insulator (MOSOI) structures were fabricated to study the effect caused by reactive ion etching (RIE) and sacrificial oxidation process on silicon-on-insulator (SOI) layer. The MOSOI capacitors with an etch-damaged SOI layer were characterized by capacitance-voltage (C-V) measurements and compared to the sacrificial oxidation treated samples and the reference samples without etching treatment. The measured C-V curves were compared to the numerical results from 2-dimensional (2-D) simulations. The measurements revealed that the profile of C-V curves significantly changes depending on the SOI surface condition of the MOSOI capacitors. The shift in the measured C-V curves, due to the difference of the fixed oxide charge ($Q_f$), together with the numerical simulation analysis and atomic force microscopy (AFM) analysis, allowed extracting the fixed oxide charges ($Q_f$) in the structures as well as 2-D carrier distribution profiles.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2011년도 제40회 동계학술대회 초록집
• /
• pp.110-110
• /
• 2011

현재 전력 반도체는 신재생/대체 에너지 시스템, 자동차/전기자동차, 디스플레이/LED 드라이브 IC 등과 같이 산업용뿐만 아니라 가정용에서도 그 수요가 급증하고 있다. 이러한 전력 반도체는 각 시스템에서 전력 변환, 분배 및 관리를 하는 역할을 하게 되는데, 이러한 전력 시스템에 적용되기 위해서는 고속 스위칭, 낮은 전력 손실 및 발열, 소형화 등의 특성이 요구되어진다. 이러한 특성을 만족하기 위해 현재 전력반도체는 수평형 소자에서 수직 형태로의 구조적 변경을 꽤하고 있으며, 또한 수직형 구조에서도 더욱 소형화와 고밀도 전류, 낮은 전력 손실 특성을 구현하기 위해 여러 가지 형태의 어레이 기술을 개발하고 있다. 본 연구에서는 사각 형태의 어레이 (square array, mesh type)를 가지는 수직형 TDMOS (Trench double diffused metal oxide effect transistor)에서 트렌치 부분을 중심으로 액티브 영역과 그 외각 영역의 도핑 농도와 접합 깊이의 변화에 따른 전기적 특성 변화를 파악함으로써 TDMOS의 안정적인 구동 영역을 확보하기 위한 연구를 수행하였다. 본 연구는 silvaco 시뮬레이션 툴을 이용하여 실제 소자 제작 공정과 유사한 형태로의 공정을 가상적으로 진행하고, 액티브 영역과 그 외각 영역의 도핑 및 접합 깊이를 결정하는 이온 주입량과, 후속 열처리의 온도와 시간 등을 변화함으로써 그 전기적 특성을 상호 비교하였다.

• 한국재료학회:학술대회논문집
• /
• 한국재료학회 2012년도 춘계학술발표대회
• /
• pp.100.2-100.2
• /
• 2012

Surface texturing of crystalline silicon is carried out in alkaline solutions for anisotropic etching that leads to random pyramids of about $10{\mu}m$ in size. Recently textured pyramids size gradually reduced using new solution. In this paper, we investigated that texture pyramids size had an impact on emitter property and front electrode (Ag) contact. To make small (${\sim}3{\mu}m$) and large (${\sim}10{\mu}m$) pyramids size, texturing times control and one side texturing using a silicon nitride film were carried out. Then formation and quality of POCl3-diffused n+ emitter in furnace compare with small and large pyramids by using SEM images, simulation (SILVACO, Athena module) and emitter saturation current density (J0e). After metallization, Ag contact resistance was measured by transfer length method (TLM) pattern. And surface distributions of Ag crystallites were observed by SEM images. Also, performance of cell which is fabricated by screen-printed solar cells is compared by light I-V.

• 대한전기학회논문지:전기물성ㆍ응용부문C
• /
• 제52권10호
• /
• pp.464-468
• /
• 2003

The double layers of $SiO_2$/$Si_3$$N_4$ have superior charge storage stability than a single layer of $SiO_2$. Many researchers are very interested in the charge storage mechanism of $SiO_2$/$Si_3$$N_4$ [1,2]. In this paper, the electrical characteristics of thermal oxide and atmospheric pressure chemical vapor deposition (APCVD) of $Si_4$$N_4$ have been investigated and explained using high frequency capacitance-voltage measurements. Additionally, this paper will describe capacitance-voltage characteristics for double layers of $SiO_2$/$Si_4$$N_4$ by "Athena", a semiconductor device simulation tool created by Silvaco, Inc.vaco, Inc.