• 한국전기전자재료학회논문지
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• 제24권2호
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• pp.112-115
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• 2011

To stabilize the electric characteristic of Silicon Thin Film Transistor, reducing the current leakage is most important issue. To reduce the current leakage, many ideas were suggested. But the increase of mask layer also increased the cost. On this research Bird's Beak process was use to present element. Using Silvaco simulator, it was proven that it was able to reduce current leakage without mask layer. As a result, it was possible to suggest the structure that can reduce the current leakage to 1.39nA without having mask layer increase. Also, I was able to lead the result that electric characteristic (on/off current ratio) was improved compare from conventional structure.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.579-580
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• 2006

Simple nonoverlapped source/drain-to-gate MOSFETs to suppress GIDL (gate-induced drain leakage) is simulated with SILVACO simulation tool. Changing spacer thickness for adjusting length of Drain to Gate nonoverlapped region, this simulation observes on/off characteristic of nonoverlapped source/drain-to-gate MOSFETs. Off current is dramatically decreased with S/D to gate nonoverlapped length increasing. The result shows that maximum on/off current ratio is achieved by adjusting nonoverlapped length.

• 전기전자학회논문지
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• 제17권2호
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• pp.129-134
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• 2013

For the conventional power metal-oxide semiconductor field-effect transistor (MOSFET) device structure, there exists a tradeoff relationship between specific on-resistance ($R_{ON.SP}$) and breakdown voltage ($V_{BR}$). In order to overcome the tradeoff relationship, a uniform super-junction (SJ) trench metal-oxide semiconductor field-effect transistor (TMOSFET) structure is studied and designed. The structure modeling considering doping concentrations is performed, and the distributions at breakdown voltages and the electric fields in a SJ TMOSFET are analyzed. The simulations are successfully optimized by the using of the SILVACO TCAD 2D device simulator, Atlas. In this paper, the specific on-resistance of the SJ TMOSFET is successfully obtained 0.96 $m{\Omega}{\cdot}cm^2$, which is of lesser value than the required one of 1.2 $m{\Omega}{\cdot}cm^2$ at the class of 100 V and 100 A for BLDC motor.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.55-58
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• 2000

SiGe heterojuction bipolar transistors (HBT) have been studied and applied for advanced high speed integrated circuits. Device characteristics of SiGe HBT depending on the Ge profile of the transistor base region have been analysed using a device simulator, ATLAS/BLAZE. The models and parameters have been calibrated to the measured characteristics of the device, having a trapeziodal base profile, including the cut-off frequency of 45GHz and the dc current gain of 200. The Ge concentration which increases linearly, exponentially, or root-functionally from the emitter-base junction to the base-collector junction, has been tried to find out the influence on the device characteristics. The cut-off frequency and gain rather strongly depends on the exponential and root-functional Ge base profiles, respectively.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.149-150
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• 2005

Thyristor breakdown voltage variation acceleration aging test was investigated. The breakdown voltage was deceased after 1000 hours acceleration aging test. It temperature rising caused by electric field concentration at the edge beveling region of the thyristor was confirmed using Silvaco device simulation. The local temperature rising is driving force for the defect propagation. Consequently, propagated defects of the beveling region seems to decrease thyristor's breakdown voltage.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.308-308
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• 2010

태양전지에서는 표면조직화를 통하여 빛을 좀 더 효과적으로 이용하고자 한다. 따라서 표면 조직화를 하지 않은 평면구조의 태양전지와 표면조직화를 실시한 태양전지의 광학적 특성을 TCAD simulation tool인 SILVACO를 이용하여 각각의 구조에 따른 특성을 분석하고자 한다. 이를 위하여 표면조직화를 실시한 구조와 실시하지 않은 구조별로 입사되는 빛의 경로추적, 빛의 세기와 각도, 파장대역별로 생성되는 QE, 그리고 입사된 빛에 의한 광생성 전류 분포와 같은 광학적 특성을 simulation할 뿐만 아니라 이에 따른 개방전압 및 단락전류와 같은 전기적 특성 분석을 통하여 효과적인 표면조직화 구조를 제시하고자 한다.

• 센서학회지
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• 제8권3호
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• pp.283-290
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• 1999

본 연구에서는 고효율 단결정 실리콘 태양전지의 제작방법인 PERL방식을 사용하여 비저항이 $0.1{\sim}2{\Omega}{\cdot}cm$을 갖는 (100)면의 p형실리콘 기판으로 $n^+/p/p^+$ 접합의 태양전지를 제작하였다. 이를 위해 웨이퍼의 절단, KOH을 사용한 역피라미드 모양으로의 에칭, 인과붕소의 도핑, 반사방지막과 전극의 증착 및 열처리 등의 공정을 행하였다. 이때 소자표면의 광학적인 특성과 도핑농도가 저항값에 미치는 영향을 조사하고, Silvaco로 $n^+$도핑에 대한 확산 깊이와 도핑농도를 시뮬레이션하여 측정치와 비교하였다. AM(air mass) 1.5 조건하에서 입사되는 빛의 세기가 $100\;mW/cm^2$인 경우의 단락전류는 43 mA, 개방전압은 0.6 V, 그리고 충실도는 0.62였다. 이때 제작된 태양전지의 광전변환효율은 16%였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.33-33
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• 2009

Silicon nano-structures have great potential in bionic sensor applications. Atomic force microscopy (AFM) anodic oxidation have many advantages for the nanostructure fabrication, such as simple process in atmosphere at room temperature, compatibility with conventional Si process. In this work, we fabricated simple FET structures with channel width W~ 10nm (nanowire) and $1{\mu}m$ (nano-ribbon) on ~10, 20 and 100nm-thinned silicon-on-insulator (SOI) wafers in order to investigate the surface effect on the transport characteristics of nano-channel. For further quantitative analysis, we carried out the 2D numerical simulations to investigate the effect of channel surface states on the carrier distribution behavior inside the channel. The simulated 2D cross-sectional structures of fabricated devices had channel heights of H ~ 10, 20, and 100nm, widths of L ~ $1{\mu}m$ and 10nm respectively, where we simultaneously varied the channel surface charge density from $1{\times}10^{-9}$ to $1{\times}10^{-7}C/cm2$. It has been shown that the side-wall charge of nanowire channel mainly affect the I-V characteristics and this was confirmed by the 2D numerical simulations.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.605-608
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• 2004

A $Pt/Al_xGa_{l-x}N$ Schottky type Ultra-violet photodetector was modeled and simulated using the commercial SILVACO software program. In the carrier transport, we applied field model and other analytic model to determine the electron saturation velocity and low field mobility for GaN and $Al_xGa_{l-x}N$. A C-Interpreter function was defined to described the mole-fraction for the ternary compound semiconductor such as $Al_xGa_{l-x}N$. As comparing the simulated and experimental results, we found that the simulated result for type-1 has $15.9 nA/cm^2$ of leakage current at 5V. We confirmed a good agreement of photo-current in the UV Photo-detector, while applying the absorption coefficient and reflective index of active $Al_xGa_{l-x}N$ and other layers. There had been an intensive search for the proper refractive indices of the layers.

• Transactions on Electrical and Electronic Materials
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• 제17권6호
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• pp.329-334
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• 2016

In this work, the temperature dependence of electrical parameters of nanoscale SOI (silicon-on-insulator) TG (triple gate) n-FinFET (n-channel Fin field effect transistor) was investigated. Numerical device simulator $ATLAS^{TM}$ was used to construct, examine, and simulate the structure in three dimensions with different models. The drain current, transconductance, threshold voltage, subthreshold swing, leakage current, drain induced barrier lowering, and on/off current ratio were studied in various biasing configurations. The temperature dependence of the main electrical parameters of a SOI TG n-FinFET was analyzed and discussed. Increased temperature led to degraded performance of some basic parameters such as subthreshold swing, transconductance, on-current, and leakage current. These results might be useful for further development of devises to strongly down-scale the manufacturing process.