• Journal of Sensor Science and Technology
• /
• v.4 no.3
• /
• pp.80-88
• /
• 1995

This paper presents the fabrication of a metal-insulator-metal(MIM) antifuse structure consisting of insulators sandwiched between top electrode, Al, and bottom electrode, TiW and additionally studies on antifuse properties depending on the condition of insulator. The intermetallic insulators, prepared by means of sputter, comprised of silicon oxide and tantalum oxide. In such an antifuse structure, silicon oxide layer is utilized to decrease the leakage current and tantalum oxide layer, of which the dielectric strength is lower than that of silicon oxide, is also utilized to lower the breakdown voltage near 10V. Finally sufficient low leakage current, below 1nA, and low programming voltage, about 9V, could be obtained in antifuse device comprising $Al/Ta_{2}O_{5}(10nm)/SiO_{2}(10nm)/TiW$ structure and OFF resistance of 3$3.65M{\Omega}$ and ON resistance of $7.26{\Omega}$ could be also obtained. This $Ta_{2}O_{5}/SiO_{2}$ based antifuse structures will be promising for highly reliable programmable device.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.5 no.2
• /
• pp.100-108
• /
• 1995

Heat transfer plays a critical role in determining interface location and shape in ZMR process, which is used for the fabrication of silicon - on - insulator structure. In this work, the two - dimensional pseudo - steady - state ZMR model has been developed that can simulate the heat transfer process during ZMR process. It contains the radiation, convection and conduction heat transfer and determines the interface shapes. Numerical solutions from the model include flow field in the molten zone, temperature field in the full SOl structure and the location of solid/liquid interface in the silicon thin film and silicon substrate. We examined the effects of the various system parameters on the temperature profiles and the interface shape.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.1 no.1
• /
• pp.20-30
• /
• 2001

A 1.8V $650{\;}\textrm{mm}^2$ 4Gb DRAM having $0.10{\;}\mu\textrm{m}^2$ cell size has been successfully developed using 0.11 $\mu\textrm{m}$DRAM technology. Considering manufactur-ability, we have focused on developing patterning technology using KrF lithography that makes $0.11{\;}\mu\textrm{m}$ DRAM technology possible. Furthermore, we developed novel DRAM technologies, which will have strong influence on the future DRAM integration. These are novel oxide gap-filling, W-bit line with stud contact for borderless metal contact, line-type storage node self-aligned contact (SAC), mechanically stable metal-insulator-silicon (MIS) capacitor and CVD Al process for metal inter-connections. In addition, 80 nm array transistor and sub-80 nm memory cell contact are also developed for high functional yield as well as chip performance. Many issues which large sized chip often faces are solved by novel design approaches such as skew minimizing technique, gain control pre-sensing scheme and bit line calibration scheme.

• Journal of IKEEE
• /
• v.1 no.1 s.1
• /
• pp.1-10
• /
• 1997

It is well-known that rectangular bulk-Si sensors prepared by etch or epi etch-stop micromachining technology are already in practical use today, but the conventional bulk-Si sensor shows some drawbacks such as large chip size and limited applications as silicon sensor device is to be miniaturized. We consider a circular-shape SOI(Silicon-On-Insulator) micro-cavity technology to facilitate multiple sensors on very small chip, to make device easier to package than conventional sensor like pressure sensor and to provide very high over-pressure capability. This paper demonstrates the cross-functional results for stress analyses(targeting $5{\mu}m$ deflection and 100MPa stress as maximum at various applicable pressure ranges), for finding permissible diaphragm dimension by output sensitivity, and piezoresistive sensor theory from two-type SOI structures where the double SOI structure shows the most feasible deflection and small stress at various ambient pressures. Those results can be compared with the ones of circular-shape bulk-Si based sensor$^{[17]}. The SOI micro-cavity formed the sensors is promising to integrate with calibration, gain stage and controller unit plus high current/high voltage CMOS drivers onto monolithic chip.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2003.07a
• /
• pp.622-625
• /
• 2003

The dependence of stress-induced leakage current on LTPS TFTs was characterized in this study. The impacts of poly-Si crystallization, gate insulator, impurity activation, hydrogenation process and electrostatic discharge damage were investigated. It was observed more TFTs instable characteristic under those process-assisted processes. According to the LTPS roadmap, smaller geometric and low temperature process were the future trend and the stress-induced leakage current should be worthy of remark.

• Transactions on Electrical and Electronic Materials
• /
• v.14 no.5
• /
• pp.250-253
• /
• 2013

In this paper, we fabricated 3D pillar type silicon-oxide-nitride-oxide-silicon (SONOS) devices for high density flash applications. To solve the limitation between erase speed and data retention of the conventional SONOS devices, bandgap-engineered (BE) tunneling oxide of oxide-nitride-oxide configuration is integrated with the 3D structure. In addition, the tunneling oxide is modulated by another method of $N_2$ ion implantation ($N_2$ I/I). The measured data shows that the BE-SONOS device has better electrical characteristics, such as a lower threshold voltage ($V_{\tau}$) of 0.13 V, and a higher $g_{m.max}$ of 18.6 ${\mu}A/V$ and mobility of 27.02 $cm^2/Vs$ than the conventional and $N_2$ I/I SONOS devices. Memory characteristics show that the modulated tunneling oxide devices have fast erase speed. Among the devices, the BE-SONOS device has faster program/erase (P/E) speed, and more stable endurance characteristics, than conventional and $N_2$ I/I devices. From the flicker noise analysis, however, the BE-SONOS device seems to have more interface traps between the tunneling oxide and silicon substrate, which should be considered in designing the process conditions. Finally, 3D structures, such as the pillar type BE-SONOS device, are more suitable for next generation memory devices than other modulated tunneling oxide devices.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
• /
• 2006.10a
• /
• pp.198-201
• /
• 2006

In this paper, we fabricated drag force type and pressure difference type gas flow sensor with dry etching technology which used Deep RIE(reactive ion etching) and etching stop technology which used SOI(silicon-on-insulator). we fabricated four kinds of sensor, which are cantilever, paddle type, diaphragm, and diaphragm with orifice type. Both cantilever and paddle type flow sensors have similar sensitivity as 0.03mV/V kPa. Sensitivity of the fabricated diaphragm and diaphragm with orifice type sensor were relatively high as about 3.5mV/V kPa, 1.5mV/V kPa respectively.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.5 no.3
• /
• pp.187-194
• /
• 2005

An analysis of the 1/f or flicker noise in FD n-channel Double Gate SOI MOSFET is proposed. In this paper, the variation of power spectral density (PSD) of the equivalent noise voltage and noise current with respect to frequency, channel length and gate-to-source voltage at various temperatures and exponent $C(i.e\;1/f^c$ is reported. The temperature is varied 125 K from to room temperature. The variation of PSD with respect to channel length down to $0.1{\mu}m$ technology is considered. It is analyzed that l/f noise in FD n-channel Double Gate SOI MOSFET is due to both carrierdensity fluctuations and mobility-fluctuations. But controversy still exits to its origin.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
• /
• 2006.10a
• /
• pp.10-13
• /
• 2006

This paper describes on the fabrication and characteristics of a 3C-SiC (Silicon Carbide) micro pressure sensor for harsh environment applications. The implemented micro pressure sensor used 3C-SiC thin-films heteroepitaxially grown on SOI (Si-on-insulator) structures. This sensor takes advantages of the good mechanical properties of Si as diaphragms fabricated by D-RIE technology and temperature properties of 3C-SiC piezoresistors. The fabricated pressure sensors were tasted at temperature up to $250^{\circ}C$ and indicated a sensitivity of 0.46 mV/V*bar at room temperature and 0.28 mV/V*bar at $250^{\circ}C$. The fabricated 3C-Sic/SOI pressure sensor presents a high-sensitivity and excel lent temperature stability.

• Journal of the Optical Society of Korea
• /
• v.18 no.2
• /
• pp.101-109
• /
• 2014

In this paper, four apodization functions are proposed for silicon-on-insulator (SOI) strip waveguides with sidewall-corrugated gratings. The effects of apodization functions on the full width at half maximum (FWHM), the side-lobe level, and the reflectivity of the reflection spectrum are studied using the coupled-mode theory (CMT) and the transfer-matrix method (TMM). The results show that applying proposed apodization functions creates very good filtering characteristics. Among investigated apodized waveguides, the apodization functions of Polynomial and z-power have the best performance in reducing side-lobes, where the side-lobe oscillations are entirely removed. Four functions are also used for precise adjustment of the bandwidth. Simulation results show that the minimum and maximum values of the FWHM are 0.74 nm and 8.48 nm respectively. In some investigated functions, changing the apodization parameters decreases the reflectivity which is compensated by increasing the grating length.