• Journal of the Korean institute of surface engineering
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• v.37 no.3
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• pp.164-168
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• 2004

Polycrystalline silicon thin films were deposited by inductively coupled plasma (ICP) assisted magnetron sputtering using a gas mixture of Ar and $H_2$ on a glass substrate at $250^{\circ}C$. At constant Ar mass flow rate of 10 sccm, the working pressure was changed between 10mTorr and 70mTorr with changing $H_2$ flow rate. The effects of RF power applied to ICP coil and $Ar/H_2$ gas mixing ratio on the properties of the deposited Si films were investigated. The crystallinity was evaluated by both X-ray diffraction and Raman spectroscopy. From the results of Raman spectroscopy, the crystallinity was improved as hydrogen mixing ratio was increased up to$ Ar/H_2$=10/16 sccm; the maximum crystalline fraction was 74% at this condition. When RF power applied to ICP coil was increased, the crystallinity was also increased around 78%. In order to investigate the surface roughness of the deposited films, Atomic Force Microscopy was used.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2533-2535
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• 1998

In this paper, an effect of drive-in process temperature on the residual stress profile of the p+ silicon film has been investigated. The residual stress profile has been calculated as the fourth-order polynomials. All coefficients of the polynomials have been determined from the measurement of the vertical deflections of the p+ silicon cantilevers with various thickness and the tip displacement of the p+ silicon rotating beam. From the determination results of the residual stress profile, the average stress of the film thermally oxidized at 1000 $^{\circ}C$ is 15 MPa and that of the film oxidized at 1100 $^{\circ}C$ is 25 MPa. The profile of the residual stress through the high temperature drive-in process has a steeper gradient than the other case.

• Journal of the Semiconductor & Display Technology
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• v.1 no.1
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• pp.9-13
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• 2002

A polyimide-type electrostatic chuck (ESC) was fabricated for the application of holding 8-inch silicon wafers in the oxide etching equipment. For the fabrication of the unipolar ESC, core technologies such as coating of polyimide films and anodizing treatment of aluminum surface were developed. The polyimide films were prepared on top of thin coated copper substrates for the good electrical contacts, and the helium gas cooling technique was used for the temperature uniformity of the silicon wafers. The ESC was essentially working with an unipolar operation, which was easier to fabricate and operate compared to a bipolar operation. The chucking force of the ESC has been measured to be about 580 gf when the applied voltage was 1.5 kV, which was considered to be enough force to hold wafers during the dry etching processing. The employment of the ESC in etcher system could make 8% enhancement of the wafer processing yield.

• Journal of the Korean Ceramic Society
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• v.36 no.8
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• pp.863-870
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• 1999

SOI(silicon on insulafor) was fabricated through the direct bonding using (100) Si wafer and 4$^{\circ}$off (100) Si wafer to investigate the stacking faults in silicon at the Si/SiO2 oxidized and bonded interface. The treatment time of wafer surface using MSC-1 solution was varied in order to observe the effect of cleaning on bonding characteristics. As the MSC-1 treating time increased surface hydrophilicity was saturated and surface microroughness increased. A comparison of surface hydrophilicity and microroughness with MSC-1 treating time indicates that optimum surface modified condition for time was immersed in MSC-1 for 2 min. The SOI structure directly bonded using (100) Si wafer and 4$^{\circ}$off (100) Si wafer at the room temperature were annealed at 110$0^{\circ}C$ for 30 min. Then the stacking faults at the bonding and oxidation interface were examined after the debonding. The results show that there were anomalies in the gettering of the stacking faults at the bonded region.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.481-485
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• 1987

The fabrication of a micro mass flow sensor on a silicon chip by means of micro-machining technology is described on this paper. The operation of micro mass flow sensor is based on the heat transfer from a heated chip to a fluid. The temperature differences on the chip is a measure for the flow velocity in a plane parallel with the chip surface. An anisotropic etching technigue was used for the formation of the V-type groove in this fabrication. The micro mass flow sensor is made up of two main parts ; A thin glass plate embodying the connecting parts and mass flow sensor parts in silicon chip. This sensor have a very small size and a neglible dead space. Micro mass flow sensor can fabricate on silicon chip by micro machining technology too.

• Journal of the Korean institute of surface engineering
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• v.48 no.3
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• pp.126-130
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• 2015

A high-pressure depletion method using plasma chemical vapor deposition (CVD) is often used to deposit hydrogenated microcrystalline silicon (${\mu}c-Si:H$) films of a low defect density at a high deposition rate. To understand proper deposition conditions of ${\mu}c-Si:H$ films for a high-pressure depletion method, Si films were deposited in a combinatorial way using a multi-hollow discharge plasma CVD method. In this paper the substrate temperature dependence of ${\mu}c-Si:H$ film properties are demonstrated. The higher substrate temperature brings about the higher deposition rate, and the process window of device quality ${\mu}c-Si:H$ films becomes wider until $200^{\circ}C$. This is attributed to competitive reactions between Si etching by H atoms and Si deposition.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.162-164
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• 2004

Nanocrystalline silicon(nc-Si) thin films on the silicon substrates have been prepared by pulsed laser deposition(PLD). The optical and structural properties of films have been investigated depending on deposition temperature, annealing, and oxidation process. When the deposition temperature increased, photoluminescence(PL) intensity abruptly decreased and peaks showed red shift. Annealing process could reduce the number of defect centers. Oxidation had a considerable effect upon the formation and isolation of the nanocrystals. These results indicate that the formation mechanism of Si nanocrystals grown by PLD can be explained by three steps of growth, passivating defect centers, and isolation, sequentially.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.163-166
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• 2003

The electrothermal simulation of high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) in thin Silicon on insulator (SOI) and Silicon on sapphire (SOS) for thermal conductivity and sink is performed by means of MEDICI. The finite element simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for the modeling of the thermal behavior of silicon-on-insulator (SOI) devices. In this paper, using for SOI LIGBT, we simulated electrothermal for device that insulator layer with $SiO_2\;and\;Al_2O_3$ at before and after latch up to measured the thermal conductivity and temperature distribution of whole device and verified that SOI LIGBT with $Al_2O_3$ insulator had good thermal conductivity and reliability

• Journal of the Semiconductor & Display Technology
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• v.9 no.2
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• pp.21-25
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• 2010

In response to the industrial needs for automated handling of very thin solar cell wafers, this paper presents the design concept for the individual wafer separation from the stacked wafers by utilizing continuous water jet. The experimental apparatus for automated wafer separation was constructed and it includes the water jet system and the microprocessor controlled wafer stack advancing system. Through a series of tests, the performance of the proposed design is quantified into the success rate of single wafer separation and the rapidity of processing wafer stack. Also, the inclination angle of wafer equipped cartridge and the water jet flowrate are found to be important parameters to be considered for process optimization. The proposed design shows the concept for fast and efficient processing of wafer separation and can be implemented in the automated manufacturing of silicon based solar cell wafers.

• Transactions on Electrical and Electronic Materials
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• v.16 no.2
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• pp.62-64
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• 2015

We have investigated zinc tin oxide (ZTO) thin films under various silicon ratios. ZTO TFTs were fabricated by solution processing with the bottom gate structure. Furthermore, annealing process was performed at different temperatures in various annealing conditions, such as air, vacuum and wet ambient. Completed fabrication of ZTO TFT, and the performance of TFT has been compared depending on the annealing conditions by measuring the transfer curve. In addition, structure in ZTO thin films has been investigated by X-ray diffraction spectroscopy (XRD) and Scanning electron microscope (SEM). It is confirmed that the electrical performance of ZTO TFTs are improved by adopting optimized annealing conditions. Optimized annealing condition has been found for obtaining high mobility.