• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.729-732
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• 2006

The effect of stress match between silicon nitride ($SiN_2$) and hydrogenated amorphous silicon (a-Si:H) layers on the electrical characteristics of thin-film transistors (TFTs) has been investigated. The result shows that modifying the deposition conditions of a Si:H and $SiN_2$ thin films can reduce the stress mismatch at a-Si:H/SiNx interface. Moreover, for best a-Si:H TFT characteristics, the internal stress of gate $SiN_2$ layer with slightly nitrogen-rich should be matched with that of a-Si:H channel layer. The ON current, field-effect mobility, and stability of TFTs can be enhanced by controlling the stress match between a-Si:H and gate insulator. The improvement of these characteristics appears to be due to both the decrease of the interface state density between the a-Si:H and SiNx layer, and the good dielectric quality of the bottom nitride layer.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.351.2-351.2
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• 2014

Indium tin oxide (ITO) has a lot of variations of its properties because it is basically in an amorphous state. Therefore, the differences in composition ratio of ITO can result in alteration of electrical properties. Normally, ITO is considered as transparent conductive oxide (TCO), possessing excellent properties for the optical and electrical devices. Quantitatively, TCO has transparency over 80 percent within the range of 380nm to 780nm, which is visible light although its specific resistance is less than $10-3{\Omega}/cm$. Thus, the solar cell is the best example for which ITO has perfectly matching profile. In addition, when ITO is used as transparent conductive electrode, this material essentially has to have a proper work function with contact materials. For instance, heterojunction with intrinsic thin layer (HIT) solar cell could have both front ITO and backside ITO. Because each side of ITO films has different type of contact materials, p-type amorphous silicon and n-type amorphous silicon, work function of ITO has to be modified to transport carrier with low built-in potential and Schottky barrier, and approximately requires variation from 3 eV to 5 eV. In this study, we examine the change of work function for different sputtering conditions using ultraviolet photoelectron spectroscopy (UPS). Structure of ITO films was investigated by spectroscopic ellipsometry (SE) and scanning electron microscopy (SEM). Optical transmittance of the films was evaluated by using an ultraviolet-visible (UV-Vis) spectrophotometer

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.389-392
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• 2009

Metal oxides have been proposed as an alternative channel material to hydrogenated amorphous silicon in thin film transistors (TFTs) because their higher mobility and stability make them suitable for transistor active layers. Thin films of indium zinc oxide (IZO) were deposited using a High Target Utilization Sputtering (HiTUS) system on various dielectrics, some of which were also deposited with the HiTUS. Investigations into bottom-gated IZO TFTs have found mobilities of 8 $cm^2V\;^1s^{-1}$ and switching ratios of $10^6$. There is a variation in the threshold voltage dependent on both oxygen concentration, and dielectric choice. Silica, alumina and silicon nitride produced stable TFTs, whilst hafnia was found to break down as a result of the IZO.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.5
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• pp.1013-1019
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• 2007

Amorphous silicon and silicon-nitride films were deposited using plasma-enhanced chemical vapor deposition (PECVD) method at $150^{\circ}C$. As fraction of $H_2$ in source gas was increased, characteristics of low-temperature silicon-nitride films approached those of conventional high-temperature films; the refractive index approached 1.9 and the ratio of nitrogen-hydrogen bonds to silicon-hydrogen bonds increased. And also, as fraction of $H_2$ in source gas was increased, characteristics of low-temperature silicon films approached those of conventional high-temperature films; refractive index and optical band gap approached 4.2 and 1.8 eV, and $[Si-H]/([Si-H]+[Si-H_2])$ increased. Lower RF power and process-pressure made the amorphous silicon films to be better properties. Increase of $H_2$ ratio seemed as the common factor to get reliable amorphous silicon and silicon-nitride films for thin-film-transistors (TFTs) at low temperature.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.1315-1318
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• 2004

Nano-scale fabrication of silicon substrate in an aqueous solution based on the use of atomic force microscopy was demonstrated. A specially designed cantilever with diamond tip, allowing the formation of damaged layer on silicon substrate easily by a simple scratching process (Tribo-Nanolithography, TNL), has been applied instead of conventional silicon cantilever for scanning. A slant nanostructure can be fabricated by a process in which a thin damaged layer rapidly forms in the substrate at the diamond tip-sample junction along scanning path of the tip and simultaneously the area uncovered with the damaged layer is being etched. This study demonstrates how the TNL parameters can affect the formation of damaged layer and the shape of 3-D structure, hence introducing a new process of proximal nanolithography in aqueous solution.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.820-824
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• 1992

An accurate method for extracting both Si film doping concentration and front or back silicon-to-oxide fixed charge density of fully depleted SOI devices is proposed. The method utilizes the current-to-voltage and capacitance-to-voltage characteristics of both SOI NMOSFET and PMOSFET which have the same doping concentration. The Si film doping concentration and the front or back silicon-to-oxide fixed charge density are extracted by mainpulating the respective threshold voltages of the SOI NMOSFET and PMOSFET according to the back surface condition (accumulation or inversion) and the capacitance-to-voltage characteristics of the SOI PMOSFET. Device simulations show that the proposed method has less than 10% errors for wide variations of the film doping concentration and the front or the back silicon-to-oxide fixed charge density.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.969-974
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• 2003

A simple and cost-effective method for the electrostatic suspension of thin plates like silicon wafers is proposed which is based on a switched voltage control scheme. It operates according to a relay feedback control and deploys only a single high-voltage power supply that can deliver a dc voltage of positive and/or negative polarity. This method possesses the unique feature that no high-voltage amplifiers are needed which leads to a remarkable system simplification relative to conventional methods. It is shown that despite the inherent limit cycle property of the relay feedback based control, an excellent performance in vibration suppression is attained due to the presence of a relatively large squeeze film damping origination from the air between the electrodes and levitated object. Using this scheme, a 4-inch silicon wafer was levitated stably with airgap variation decreasing down to 1 $\mu\textrm{m}$ at an airgap of 100 $\mu\textrm{m}$

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.4 no.2
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• pp.131-133
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• 1994

Deposition of silicon on pretreated sapphire substrates has been investigated by the liquid phase epitaxy method at low temperatures. An average 14 $\mu\textrm{m}$ thickness of silicon was grown over a large area on sapphire substrate originally coated with a much thinner silicon layer $[0.5 \mu\textrm{m} (100) Si/(1102) sapphire]$ at low temperatures from $(380^{\circ}C to 460^{\circ}C)$.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.2
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• pp.17-24
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• 2000

In this paper, the stress and transient currents associated with the on and off time of applied voltage were used to measure the density and distribution of high voltage stress induced traps in thin silicon oxide films. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform new both cathode and anode interface. The trap densities were dependent on the stress polarity. The stress generated trap distributions were relatively uniform the order of 1011~1021[states/eV/cm2] after a stress voltage. It appear that the stress and transient current that flowed when the stress voltage were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.2
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• pp.194-201
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• 2005

Nanoscale fabrication of silicon substrate in an aqueous solution based on the use of atomic force microscopy was demonstrated. A specially designed cantilever with diamond tip, allowing the formation of damaged layer on silicon substrate easily by a simple scratching process (Tribo-Nanolithography, TNL), has been applied instead of conventional silicon cantilever for scanning. A slant nanostructure can be fabricated by a process in which a thin damaged layer rapidly forms in the substrate at the diamond tip-sample junction along scanning path of the tip and simultaneously the area uncovered with the damaged layer is being etched. This study demonstrates how the TNL parameters can affect the formation of damaged layer and the shape of 3-D structure, hence introducing a new process of AFM-based nanolithography in aqueous solution.