• Transactions of Materials Processing
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• v.13 no.3
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• pp.285-289
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• 2004

Micro tensile test specimens of thin film single crystal silicon for the most useful structural materials in MEMS (Micro Electro Mechanical System) devices were fabricated using SOI (Silicon-on-Insulator) wafers and MEMS processes. Dimensions of micro tensile test specimens were thickness of $7\mu\textrm{m}$, width of 50~$350\mu\textrm{m}$, and length of 2mm. Top and bottom silicon were etched using by deep RIE (Reactive Ion Etching). Thin film aluminum markers on testing region of specimens with width of $5\mu\textrm{m}$, lengths of 30~$180\mu\textrm{m}$ and thickness of 200 nm for measuring tensile strain were fabricated by aluminum wet etching method. Fabricated side wall angles of aluminum marker were about $45^{\circ}~50^{\circ}$. He-Ne laser with wavelength of 633nm was used for checking fringed patterns.

• Korean Journal of Materials Research
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• v.29 no.9
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• pp.547-552
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• 2019

In the present study, the thermal conductivity of a silicon nitride($Si_3N_4$) thin-film is evaluated using the dual-wavelength pump-probe technique. A 100-nm thick $Si_3N_4$ film is deposited on a silicon (100) wafer using the radio frequency plasma enhanced chemical vapor deposition technique and film structural characteristics are observed using the X-ray reflectivity technique. The film's thermal conductivity is measured using a pump-probe setup powered by a femtosecond laser system of which pump-beam wavelength is frequency-doubled using a beta barium borate crystal. A multilayer transient heat conduction equation is numerically solved to quantify the film property. A finite difference method based on the Crank-Nicolson scheme is employed for the computation so that the experimental data can be curve-fitted. Results show that the thermal conductivity value of the film is lower than that of its bulk status by an order of magnitude. This investigation offers an effective way to evaluate thermophysical properties of nanoscale ceramic and dielectric materials with high temporal and spatial resolutions.

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.46.1-46.1
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• 2010

Surface passivation of crystalline silicon(c-Si) surface with a-Si:H thin films has been investigated by using quasi-steady-state photo conductance(QSSPC) measurements. Analyzing the influence of a-Si:H film thickness, process gas ratio, deposition temperature and post annealing temperature on the passivation properties of c-Si, we optimized the passivation conditions at the substrate temperature of $200-250^{\circ}C$. Best surface passivation has been obtained by post-deposition annealing of a-Si:H film layer. Post annealing around the deposition temperature was sufficient to improve the surface passivation for silicon substrates. We obtained effective carrier lifetimes above 5.5 ms on average.

• KIEE International Transactions on Electrophysics and Applications
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• v.5C no.2
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• pp.76-80
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• 2005

In this paper, a miniaturized ring hybrid circuit is characterized based on a thin film microstrip (TFMS) on low-resistivity silicon. In order to obtain low-loss characteristics, a polyimide layer with 50 $\mu$m thickness is spin-coated onto the silicon to be used for the substrate. First, propagation characteristics of TFMS lines consisting of the ring hybrid circuit are presented. Then, a ring hybrid circuit based on TFMS is featured by employing the triple concentric circle approach for miniaturization. Triple concentric circle lines with $\lambda$$_{g}$/4 or 3$\lambda$$_{g}$/4 line lengths are implemented on the surface of the polyimide by circularly meandering to reduce the circuit size of the designed ring hybrid. Good agreement between measured and simulated results is obtained.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.371-371
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• 2010

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the MEMS implementation with nano structure. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $41{\AA}$, which have the gate area $10^{-3}cm^2$. The stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• ETRI Journal
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• v.28 no.1
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• pp.45-50
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• 2006

An RC oscillator using amorphous silicon thin film transistors was developed. The oscillation frequency and its dependence on resistance and bias voltage were studied. The frequency was controlled by adjusting the feedback resistance of the oscillator. The highest measured frequency of the oscillator was around 140 kHz, which is acceptable for low-end radio frequency identification (RFID). Since a low-end RFID circuit needs low cost and a simple process, an amorphous silicon oscillator is suitable.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.428-431
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• 2003

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $113.4{\AA}$ and $814{\AA}$, which have the gate area 10-3cm2. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.201-204
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• 2001

In this paper, for modeling of electrical characteristics in Poly Silicon Thin Film Transistors with process parameters set up optimum values, So, the I-V characteristics of poly silicon TFT parameters are examined and simulated in terms of the variations in process parameter. And these results compared and analyzed simulation values with examination value. The simulation program for characteristic analysis used SUPREM IV for processing, Matlab for modeling by mathematics, and SPICE for electric characteristic of devices. Input parameter for simulation characteristics is like condition of device process sequence, these electric characteristic of $I_D-V_D$ $I_D-V_G$, variations of grain size. The Gate oxide thickness of poly silicon are showed similar results between real device characteristics and simulation characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.201-204
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• 2001

In this paper, for modeling of electrical characteristics in Poly Silicon Thin Film Transistors with process parameters set up optimum values. So, the I-V characteristics of poly silicon TFT parameters are examined and simulated in terms of the variations in process parameter. And these results compared and analyzed simulation values with examination value. The simulation program for characteristic analysis used SUPREM IV for processing, Matlab for modeling by mathematics, and SPICE for electric characteristic of devices. Input parameter for simulation characteristics is like condition of device process sequence, these electric characteristic of I$_{D}$-V$_{D}$, I$_{D}$-V$_{G}$, variations of grain size. The Gate oxide thickness of poly silicon are showed similar results between real device characteristics and simulation characteristics.ristics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.4
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• pp.255-260
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• 1998

Behavior of solid phase crystallizations (SPC) of RF sputtered and LPCVD amorphous hydrogenated silicon film were investigated. LPCVD films showed the higher degree of crystallinity and larger grain size than sputtered films. The applicable degree of crystallinity was also obtained from sputtered films. The deposition method of amorphous silicon film influenced the behavior of post annealing SPC. Observed degree of crystallinity of sputtered films strongly depended on the partial pressure of hydrogen in deposition. The higher deposition temperature of sputtering provided the better crystallinity after SPC. Due to the high degree of poly-crystallinity, the retardation of larger grain growth was observed on sputtering film.