• Title/Summary/Keyword: Silicon thickness

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A Study on Fabrication of Piezorresistive Pressure Sensor (벌크 마이크로 머쉬닝에 의한 다결정 실리콘 압력센서 제작 관한 연구)

  • 임재홍;박용욱;윤석진;정형진;윤영수
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1999.05a
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    • pp.677-680
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    • 1999
  • Rapid developing automation technology enhances the need of sensors. Among many materials, silicon has the advantages of electrical and mechanical property, Single-crystalline silicon has different piezoresistivity on 야fferent directions and a current leakage at elevated temperature, but poly-crystalline silicon has the possibility of controling resistivity using dopping ions, and operation at high temperature, which is grown on insulating layers. Each wafer has slightly different thicknesses that make difficult to obtain the precisely same thickness of a diaphragm. This paper deals with the fabrication process to make poly-crystalline silicon based pressure sensors which includes diaphragm thickness and wet-etching techniques for each layer. Diaphragms of the same thickness can be fabricated consisting of deposited layers by silicon bulk etching. HF etches silicon nitride, HNO$_3$+HF does poly -crystalline silicon at room temperature very fast. Whereas ethylenediamice based etchant is used to etch silicon at 11$0^{\circ}C$ slowly.

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Study on Thickness of Porous Silicon Layer According to the Various Anodization Times

  • Jang, Seunghyun
    • Journal of Integrative Natural Science
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    • v.3 no.4
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    • pp.206-209
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    • 2010
  • As the etching time is varied, the change of thickness of the porous silicon layers was successfully investigated. The thickness of the PSi layer as a function of anodization time for a p-type substrate that is etched at a constant current density of 50 $mA/cm^2$ in a 35% hydrofluoric acid solution shows a linear relationship between the etching time and the thickness of the PSi layer.

Development of Real Time Thickness Measurement System of Thin Film for 12" Wafer Spin Etcher (12" 웨이퍼 Spin etcher용 실시간 박막두께 측정장치의 개발)

  • 김노유;서학석
    • Journal of the Semiconductor & Display Technology
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    • v.2 no.2
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    • pp.9-15
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    • 2003
  • This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12" silicon wafer for spin etcher. Halogen lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and adaptive filtering. Test wafers with three kinds of priori-known films, polysilicon(300 nm), silicon-oxide(500 nm) and silicon-oxide(600 nm), are measured while the wafer is spinning at 20 Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 0.8% error.rror.

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Gate Insulator 두께 가변에 따른 TFT소자의 전기적 특성 비교분석

  • Kim, Gi-Yong;Jo, Jae-Hyeon;Lee, Jun-Sin
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.11a
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    • pp.39-39
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    • 2009
  • We fabricated p-channel TFTs based on poly Silicon. The 35nm thickness silicon dioxide layer structure got higher $I_{on}/I_{off}$ ratio, field-effect Mobility and output current than 10nm thickness. And 35nm layer showed low leakage current and threshold voltage. So, 35nm thickness silicon dioxide layer TFTs are faster reaction speed and lower power consumption than 10nm thickness.

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Analytical Threshold Voltage Modeling of Surrounding Gate Silicon Nanowire Transistors with Different Geometries

  • Pandian, M. Karthigai;Balamurugan, N.B.
    • Journal of Electrical Engineering and Technology
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    • v.9 no.6
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    • pp.2079-2088
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    • 2014
  • In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET. Threshold voltage roll-off and DIBL characteristics of these devices are also studied. Proposed models are clearly validated by comparing the simulations with the TCAD simulation for a wide range of device geometries.

Chemical and Physical Properties of Porous Silicon

  • Jang, Seunghyun
    • Journal of Integrative Natural Science
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    • v.4 no.1
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    • pp.1-6
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    • 2011
  • The properties of porous silicon, such as substrate properties, porosity, thickness, refractive index, surface area, and optical properties of porous silicon were reviewed. Some properties, such as porosity, refractive index, thickness, pore diameter, multi-structures, and optical properties, are strongly dependent on the anodization process parameters. These parameters include HF concentration, current density, anodization time, and silicon wafer type and resistivity.

Evaluation of Flexural Strength of Silicon Die with Thickness by 4 Point Bending Test (4점굽힘시험에 의한 실리콘 다이의 두께에 따른 파단강도 평가)

  • Min, Yoon-Ki;Byeon, Jai-Won
    • Journal of the Microelectronics and Packaging Society
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    • v.18 no.1
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    • pp.15-21
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    • 2011
  • In this study, flexural strength and fracture behavior of silicon die from single crystalline silicon wafer were investigated as a function of thickness. Silicon wafers with various thickness of 300, 200, 180, 160, 150, and 100 ${\mu}m$ were prepared by mechanical grinding and polishing of as-saw wafers. Flexural strength of 40 silicon dies (size: 62.5 mm${\times}$4 mm) from each wafer was measured by four point bending test, respectively. For statistical analysis of flexural strength, shape factor(i.e., Weibull modulus) and scale factor were determined from Weibull plot. Flexural strength reflecting both statistical fracture probability and size (thickness) effect of brittle silicon die was obtained as a linear function of die thickness. Fracture appearance was discussed in relation with measured fracture strength.

A effect of the back contact silicon solar cell with surface texturing size and density (표면 텍스쳐링 크기와 밀도가 후면 전극 실리콘 태양전지에 미치는 영향)

  • Jang, Wanggeun;Jang, Yunseok;Pak, Jungho
    • 한국신재생에너지학회:학술대회논문집
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    • 2011.05a
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    • pp.112.1-112.1
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    • 2011
  • The back contact solar cell (BCSC) has several advantages compared to the conventional solar cell since it can reduce grid shadowing loss and contact resistance between the electrode and the silicon substrate. This paper presents the effect of the surface texturing of the silicon BCSC by varying the texturing depth or the texturing gap in the commercially available simulation software, ATHENA and ATLAS of the company SILVACO. The texturing depth was varied from $5{\mu}m$ to $150{\mu}m$ and the texturing gap was varied from $1{\mu}m$ to $100{\mu}m$ in the simulation. The resulting efficiency of the silicon BCSC was evaluated depending on the texturing condition. The quantum efficiency and the I-V curve of the designed silicon BCSC was also obtained for the analysis since they are closely related with the solar cell efficiency. Other parameters of the simulated silicon BCSC are as follows. The substrate was an n-type silicon, which was doped with phosphorous at $6{\times}10^{15}cm^{-3}$, and its thickness was $180{\mu}m$, a typical thickness of commercial solar cell substrate thickness. The back surface field (BSF) was $1{\times}10^{20}\;cm^{-3}$ and the doping concentration of a boron doped emitter was $8.5{\times}10^{19}\;cm^{-3}$. The pitch of the silicon BCSC was $1250{\mu}m$ and the anti-reflection coating (ARC) SiN thickness was $0.079{\mu}m$. It was assumed that the texturing was anisotropic etching of crystalline silicon, resulting in texturing angle of 54.7 degrees. The best efficiency was 25.6264% when texturing depth was $50{\mu}m$ with zero texturing gap in case of low texturing depth (< $100{\mu}m$).

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Evaluation of Fracture Strength of Silicon Die with Surface Condition by Ball Breaker Test (볼브레이커시험에 의한 실리콘 다이의 표면조건에 따른 파단강도 평가)

  • Byeon, Jai-Won
    • Journal of the Korean Society for Heat Treatment
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    • v.26 no.4
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    • pp.178-184
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    • 2013
  • The effects of thickness and surface grinding condition on the fracture strength of Si wafer with a thickness under $100{\mu}m$ were investigated. Fracture strength was measured by ball breaker test for about 330 dies (size: $4mm{\times}4mm$) per each wafer. For statistical analysis of the fracture strength, scale factor was determined from Weibull plot. Ball breaker fracture strength was observed to increase with decreasing thickness of silicon die. For the silicon dies of different surface conditions, ball breaker fracture strength was high in the order of polished, ground (#4800), and ground (#320 grit) specimen. Probabilistic fracture strength (i.e., scale factor) increased with decreasing surface roughness of silicon die.

Effect of Film Thickness on the Tribological Characteristics of Zdol Lubricant on Silicon Surface

  • Kim, Yong-Sik;Yang, Ji-Chul;Kim, Dae-Eun
    • International Journal of Precision Engineering and Manufacturing
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    • v.5 no.1
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    • pp.13-18
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    • 2004
  • In precision mechanical components that experience sliding, it is important to reduce the friction to minimize surface damage. Particularly, new lubrication methods are needed to reduce friction in silicon based micro-systems applications. In this work, the tribological characteristics of PFPE (Perfluoropolyether) Zdol lubricant on silicon were investigated based on the thickness of the film. The lubricant was coated on silicon wafer specimens by the dip coating method. It was shown that the friction coefficient as well as stiction decreased as the thickness of the film increased. The results of this work may be applied to improve the tribological performance of silicon based micro-system components.