• Journal of Integrative Natural Science
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• v.2 no.3
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• pp.202-206
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• 2009

Optical images based on the porous silicon exhibiting photoluminescence have been prepared from an electrochemical etching of n-type silicon wafer (boron-doped,<100> orientation, resistivity $1{\sim}10{\Omega}-cm$) by using a beam projector. The images remained in the substrate displayed an optical images correlating to the optical pattern and could be useful for optical data storage. This provides the ability to fabricate complex optical encoding in the surface of silicon.

• Journal of Integrative Natural Science
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• v.4 no.1
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• pp.1-6
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• 2011

The properties of porous silicon, such as substrate properties, porosity, thickness, refractive index, surface area, and optical properties of porous silicon were reviewed. Some properties, such as porosity, refractive index, thickness, pore diameter, multi-structures, and optical properties, are strongly dependent on the anodization process parameters. These parameters include HF concentration, current density, anodization time, and silicon wafer type and resistivity.

• Proceedings of the Materials Research Society of Korea Conference
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• 1993.05a
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• pp.71-71
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• 1993

• Bulletin of the Korean Chemical Society
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• v.32 no.12
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• pp.4371-4376
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• 2011

In this work, we investigate the growth behavior of silicon oxide nanowires via a solid-liquid-solid process. Silicon oxide nanowires were synthesized at $1000^{\circ}C$ in an Ar and $H_2$ mixed gas. A pre-oxidized silicon wafer and a nickel film are used as the substrate and catalyst, respectively. We propose two distinctive growth modes for the silicon oxide nanowires that both act as a unique solid-liquid-solid growth process. We named the two growth mechanisms "grounded-growth" and "branched-growth" modes to characterize their unique solid-liquid-solid growth behavior. The two growth modes were classified by the generation site of the nanowires. The grounded-growth mode in which the grown nanowires are generated from the substrate and the branchedgrowth mode where the nanowires are grown from the side of the previously grown nanowires or at the metal catalyst drop attached at the tip of the nanowire stem.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.1
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• pp.23-28
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• 2023

This paper demonstrates a novel NAND flash memory structure and annealing configuration including through-silicon via (TSV) inside the silicon substrate to improve annealing efficiency using an electro-thermal annealing (ETA) technique. Compared with the conventional ETA which utilizes WL-to-WL current flow, the proposed annealing method has a higher annealing temperature as well as more uniform heat distribution, because of thermal isolation on the silicon substrate. In addition, it was found that the annealing temperature is related to the electrical and thermal conductivity of the TSV materials. As a result, it is possible to improve the reliability of NAND flash memory. All the results are discussed based on 3-dimensional (3-D) simulations with the aid of the COMSOL simulator.

• Journal of the Korean institute of surface engineering
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• v.26 no.3
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• pp.115-120
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• 1993

Aluminum thin films were deposited on the silicon substrate by the pyrolysis of TrilsoButylAluminum (TIBA) in a cold wall LPCVD reactor. The effect of substrate on the surface topograply and the decomposition reaction was investigated. The activation energy for the decomposition of TIBA was turned out to be 1 eV from the Arrhenious plot. The surface topography of the CVD aluminum could be improved by the application of thin metal film, which was in-situ deposited on the silicon prior to CVD process.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.387-392
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• 2018

Static characteristics of SiC (silicon carbide) lateral p-i-n diodes implemented on semi-insulating substrate without an epitaxial layer are inVestigated. On-axis SiC HPSI (high purity semi-insulating) and VDSI (Vanadium doped semi-insulating) substrates are used to fabricate the lateral p-i-n diode. The space between anode and cathode ($L_{AC}$) is Varied from 5 to $20{\mu}m$ to inVestigate the effect of intrinsic-region length on static characteristics. Maximum breakdown Voltages of HPSI and VDSI are 1117 and 841 V at $L_{AC}=20{\mu}m$, respectiVely. Due to the doped Vanadium ions in VDSI substrate, diffusion length of carriers in the VDSI substrate is less than that of the HPSI substrate. A forward Voltage drop of the diode implemented on VDSI substrate is 12 V at the forward current of $1{\mu}A$, which is higher than 2.5 V of the diode implemented on HPSI substrate.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2007.04a
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• pp.78-79
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• 2007

In this study, chemical dry characteristics of silicon nitride layers were investigated in the $F_2/N_2/Ar$ remote plasma. A toroidal-type remote plasma source was used for the generation of remote plasmas. The effects of additive $N_2$ gas on the etch rates of various silicon nitride layers deposited using different deposition techniques and precursors were investigated by varying the various process parameters, such as the $F_2$ flow rate, the addition $N_2$ flow rate and the substrate temperature. The etch rates of the various silicon nitride layers at the room temperature were initially increased and then decreased with the $N_2$ flow increased, which indicates an existence of the maximum etch rates. The etch rates of the silicon oxide layers were also significantly increased with the substrate temperature increased. In the present experiments the $F_2$ gas flow, addition $N_2$ flow rate and the substrate temperature were found to be the critical parameters in determining the etch rate of the silicon nitride layers

• Proceedings of the KIEE Conference
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• 2003.10a
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• pp.297-299
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• 2003

In this paper, we present the fabrication of copper electrode array and test of electrochemical discharge machining for the fabrication of microholes on Borofloat33 glass. Copper electrode array is fabricated by the bonding of silicon upper substrate and lower substrate and copper electroplate. The silicon upper electrode having microholes fabricated by ICP-RIE is the mold of copper electroplate. The lower substrate is used as the seed layer for copper electroplate after Au - Au thermocompression bonding with the upper substrate.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.8
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• pp.1230-1235
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• 2017

We studied surface texture-etching of glass substrate by using reactive ion etching process with various working pressure (0.7~9.0 mT). With the increase in the pressure, a haze parameter, which means diffusive transmittance/total transmittance, was increased in overall wavelength regions, as measured by spectrophotometer. Also, atomic force microscopy (AFM) study also showed that the surface topography transformed from V-shaped, keen surface to U-shaped, flattened surface, which is beneficial for nanocrystalline silicon semiconductor growth with suppressing defective crack formation. The texture-etched ZnO:Al combined with textured glass exhibited pronounced haze properties that showed 60~90 % in overall spectral wavelength regions. This promising optical properties of double textured, transparent conducting substrate can be widely applied in silicon thin film photovoltaics and other optoelectronic devices.