• Title/Summary/Keyword: Silicon substrate

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The Fabrication of Four-Terminal Poly-Si TFTs with Buried Channel (Buried Channel 4단자 Poly-Si TFTs 제작)

  • Jeong, Sang-Hun;Park, Cheol-Min;Yu, Jun-Seok;Choe, Hyeong-Bae;Han, Min-Gu
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.48 no.12
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    • pp.761-767
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    • 1999
  • Poly-Si TFTs(polycrystalline silicon thin film transistors) fabricated on a low cost glass substrate have attracted a considerable amount of attention for pixel elements and peripheral driving circuits in AMLCS(active matrix liquid crystal display). In order to apply poly-Si TFTs for high resolution AMLCD, a high operating frequency and reliable circuit performances are desired. A new poly-Si TFT with CLBT(counter doped lateral body terminal) is proposed and fabricated to suppress kink effects and to improve the device stability. And this proposed device with BC(buried channel) is fabricated to increase ON-current and operating frequency. Although the troublesome LDD structure is not used in the proposed device, a low OFF-current is successfully obtained by removing the minority carrier through the CLBT. We have measured the dynamic properties of the poly-Si TFT device and its circuit. The reliability of the TFTs and their circuits after AC stress are also discussed in our paper. Our experimental results show that the BC enables the device to have high mobility and switching frequency (33MHz at $V_{DD}$ = 15 V). The minority carrier elimination of the CLBT suppresses kink effects and makes for superb dynamic reliability of the CMOS circuit. We have analyzed the mechanism in order to see why the ring oscillators do not operate by analyzing AC stressed device characteristics.

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Synthesis of Silica Aerogel and Thin Film Coating at Ambient (상입하에서의 실리카 에어로겔의 합성 및 박막코팅(I))

  • 양희선;최세영
    • Journal of the Korean Ceramic Society
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    • v.34 no.2
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    • pp.188-194
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    • 1997
  • Wet gel with surface modification by TMCS was redispersed in EtOH and redispersed silica sol for coat-ing was prepared. After spin coating of redispersed sol was conducted on silicon substrate, processes of drying(8$0^{\circ}C$) and heat treatment(>25$0^{\circ}C$) were, followed at ambient pressure. The influence of heat treat-ment of properties of film was observed, changing temperature at heat treatment. The optimum redisp-ersion condition for stable silica sol was wet gel:EtOH=1g:110$m\ell$ and the concentration and viscosity of redispersed silica sol with average particle size of 30nm were 0.11 M, 2.0-2.2 cP respectively. Crack-free thin film with the refractive index of 1.14 and thickness of 400 nm was obtained through drying at 8$0^{\circ}C$ and subsequent heat treatment at 45$0^{\circ}C$ for 2 hrs respectively after spin coating of 1500rpm, 10 times.

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A Study on the Electrical Characteristics of Different Wire Materials

  • Jeong, Chi-Hyeon;Ahn, Billy;Ray, Coronado;Kai, Liu;Hlaing, Ma Phoo Pwint;Park, Susan;Kim, Gwang
    • Journal of the Microelectronics and Packaging Society
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    • v.20 no.4
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    • pp.47-52
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    • 2013
  • Gold wire has long been used as a proven method of connecting a silicon die to a substrate in wide variety of package types, delivering high yield and productivity. However, with the high price of gold, the semiconductor packaging industry has been implementing an alternate wire material. These materials may include silver (Ag) or copper (Cu) alloys as an alternative to save material cost and maintain electrical performance. This paper will analyze and compare the electrical characteristics of several wire types. For the study, typical 0.6 mil, 0.8 mil and 1.0 mil diameter wires were selected from various alloy types (2N gold, Palladium (Pd) coated/doped copper, 88% and 96% silver) as well as respective pure metallic wires for comparison. Each wire model was validated by comparing it to electromagnetic simulation results and measurement data. Measurements from the implemented test boards were done using a vector network analyzer (VNA) and probe station setup. The test board layout consisted of three parts: 1. Analysis of the diameter, length and material characteristic of each wire; 2. Comparison between a microstrip line and the wire to microstrip line transition; and 3. Analysis of the wire's cross-talk. These areas will be discussed in detail along with all the extracted results from each type the wire.

Fabrication and Characteristics of Photoconductive Amorphous Silicon Film for Facsimile (팩시밀리용 비정질 실리콘 광도전막의 제작 및 특성)

  • Kim, Jeong-Seob;Oh, Sang-Kwang;Kim, Ki-Wan;Lee, Wu-Il
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.6
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    • pp.48-56
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    • 1989
  • Contact-type linear image sensors for facsimile have been fabricated by means of rf glow discharge decomposition method of silane. The dependence of their electrical and optical properties on rf power, $SiH_4$ flow rate, ambient gas pressure, $H_2SiH_4$ ratio and substrate temperature are described. The a-Si:H monolayer demonstriated photosensitivity of 0.85 and $I_{ph}/I_d$ ratio of 100 unger 100 lux illumination. However, this monolayer has relatively high dark current due to carrier injection from both electrodes, resulting in low $I_{ph}/I_{dd}$ ratio. To suppress the dark current we have fabricated $SiO_2/i-a-Si:H/p-a-Si:H:B$ multilayer film with blocking structure. The photocurrent of this multilayer sensor with 6 V bias became saturated ar about 20nA under 10 lux illumination, while the dark current was less than 0.2 nA. Moreover, the spectral sensitivity of the multilayer film was enhanced for short wavelength visible region, compared with that of the a-Si:H monolayer. These results show that the fabricated photocon-ductive film can be used as the linear image sensor of the facsimile.

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Graphene Transistor Modeling Using MOS Model (MOS 모델을 이용한 그래핀 트랜지스터 모델링)

  • Lim, Eun-Jae;Kim, Hyeongkeun;Yang, Woo Seok;Yoo, Chan-Sei
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.26 no.9
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    • pp.837-840
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    • 2015
  • Graphene is a single layer of carbon material which shows very high electron mobility, so many kinds of research on the devices using graphene layer have been performed so far. Graphene material is adequate for high frequency and fast operation devices due to its higher mobility. In this research, the actual graphene layer is evaluated using RT-CVD method which can be available for mass production. The mobility of $7,800cm^2/Vs$ was extracted, that is more than 7 times of that in silicon substrate. The graphene transistor model having no band gap is evaluated using both of pMOS and nMOS based on the measured mobility values. And then the response of graphene transistor model regarding to gate length and width is examined.

Practical Implementation of Memristor Emulator Circuit on Printed Circuit Board (PCB에 구현한 멤리스터 에뮬레이터 회로 및 응용)

  • Choi, Jun-Myung;Sin, SangHak;Min, Kyeong-Sik
    • Journal of IKEEE
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    • v.17 no.3
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    • pp.324-331
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    • 2013
  • In this paper, we implemented memristor emulator circuit on Printed Circuit Board (PCB) and observed the inherent pinched hysteresis characteristic of memristors by measuring the emulator circuit on PCB. The memristor emulator circuit implemented on PCB is composed of simple discrete devices not using any complicated circuit blocks thus we can integrate the memristor emulator circuits in very small layout area on Silicon substrate. The programmable gain amplifier is designed using the proposed memristor emulator circuit and verified that the amplifier's voltage gain can be controlled by programming memristance of the emulator circuit by circuit simulation. Threshold switching is also realized in the proposed emulator circuit thus memristance can remain unchanged when the input voltage applied to the emulator circuit is lower than VREF. The memristor emulator circuit and the programmable gain amplifier using the proposed circuit can be useful in teaching the device operation, functions, characteristics, and applications of memristors to students when thet cannot access to device and fabrication technologies of real memristors.

Laser Micro-machining technology for Fabrication of the Micro Thin-Film Inductors (초소형 박막 인덕터 제작을 위한 레이저 미세가공 기술 개발)

  • Ahn, Seong-Joon;Ahn, Seung-Joon;Kim, Dae-Wook;Kim, Ho-Seob;Kim, Cheol-Gi
    • Journal of the Korean Magnetics Society
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    • v.13 no.3
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    • pp.115-120
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    • 2003
  • We have developed laser micro-machining technology for fabrication of the micro thin-film inductors. After the thin layers of FM/M/FM films were coated to the silicon substrate by using the conventional sputtering method, the new laser machining was applied to the patterning process that used to be carried out by the semiconductor lithography procedure. A CW Nd:YAG laser operating in TEM$\sub$00/ mode was actively Q-switched to obtain the very short pulse of 200 ns. The laser micro-machining process with pulse energy and repetition rate have been optimized as 5 mJ/pulse and 5 kHz, respectively, to obtain the line resolution as fine as 20 $\mu\textrm{m}$.

Periodically Aligned Metal Nanoparticle Array for a Plasmonic Absorber and Its Fabrication Technique (플라즈모닉 흡수체를 위한 금속 나노입자 주기구조 제작 기술)

  • Choi, Minjung;Ryu, Yunha;Bae, Kyuyoung;Kang, Gumin;Kim, Kyoungsik
    • Korean Journal of Optics and Photonics
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    • v.28 no.6
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    • pp.361-365
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    • 2017
  • In this paper, we demonstrate a facile fabrication technique for a periodically aligned metal nanoparticle array, for a narrow-band plasmonic absorber. The metal nanoparticles are fabricated by e-beam evaporation and heat treatment processes on top of a periodic aluminum groove template. The plasmonic absorber is constructed with the transferred metal nanoparticle array, sputtered 33-nm-thick $Al_2O_3$, and 200-nm-thick metal reflector layers on silicon substrate. 46-nm-diameter and 76-nm-lattice metal-nanoparticle-array-based plasmonic absorber has performed as a narrow-band absorber with a central wavelength of 572 nm and full width at half maximum (FWHM) of 109.9 nm.

A Novel z-axis Accelerometer Fabricated on a Single Silicon Substrate Using the Extended SBM Process (Extended SBM 공정을 이용하여 단일 실리콘 기판상에 제작된 새로운 z 축 가속도계)

  • Ko, Hyoung-Ho;Kim, Jong-Pal;Park, Sang-Jun;Kwak, Dong-Hun;Song, Tae-Yong;Cho, Dong-Il;Huh, Kun-Soo;Park, Jahng-Hyon
    • Journal of Sensor Science and Technology
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    • v.13 no.2
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    • pp.101-109
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    • 2004
  • This paper presents a novel z-axis accelerometer with perfectly aligned vertical combs fabricated using the extended sacrificial bulk micromachining (extended SBM) process. The z-axis accelerometer is fabricated using only one (111) SOI wafer and two photo masks without wafer bonding or CMP processes as used by other research efforts that involve vertical combs. In our process, there is no misalignment in lateral gap between the upper and lower comb electrodes, because all critical dimensions including lateral gaps are defined using only one mask. The fabricated accelerometer has the structure thickness of $30{\mu}m$, the vertical offset of $12{\mu}m$, and lateral gap between electrodes of $4{\mu}m$. Torsional springs and asymmetric proof mass produce a vertical displacement when an external z-axis acceleration is applied, and capacitance change due to the vertical displacement of the comb is detected by charge-to-voltage converter. The signal-to-noise ratio of the modulated and demodulated output signal is 80 dB and 76.5 dB, respectively. The noise equivalent input acceleration resolution of the modulated and demodulated output signal is calculated to be $500{\mu}g$ and $748{\mu}g$. The scale factor and linearity of the accelerometer are measured to be 1.1 mV/g and 1.18% FSO, respectively.

UV Responsive Characteristics of n-Channel Schottky Barrier MOSFET with ITO as Source/Drain Contacts

  • Kim, Tae-Hyeon;Lee, Chang-Ju;Kim, Dong-Seok;Sung, Sang-Yun;Heo, Young-Woo;Lee, Jung-Hee;Hahm, Sung-Ho
    • Journal of Sensor Science and Technology
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    • v.20 no.3
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    • pp.156-161
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    • 2011
  • We fabricated a schottky barrier metal oxide semiconductor field effect transistor(SB-MOSFET) by applying indium-tin-oxide(ITO) to the source/drain on a highly resistive GaN layer grown on a silicon substrate. The MOSFET, with 10 ${\mu}M$ gate length and 100 ${\mu}M$ gate width, exhibits a threshold gate voltage of 2.7 V, and has a sub-threshold slope of 240 mV/dec taken from the $I_{DS}-V_{GS}$ characteristics at a low drain voltage of 0.05 V. The maximum drain current is 18 mA/mm and the maximum transconductance is 6 mS/mm at $V_{DS}$=3 V. We observed that the spectral photo-response characterization exhibits that the cutoff wavelength was 365 nm, and the UV/visible rejection ratio was about 130 at $V_{DS}$ = 5 V. The MOSFET-type UV detector using ITO, has a high UV photo-responsivity and so is highly applicable to the UV image sensors.