• Journal of the Korean institute of surface engineering
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• v.29 no.6
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• pp.809-815
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• 1996

$Y_2O_3$-based metal-insulator-semiconductor (MIS) structure on p-Si(100) has been studied. Films were prepared by UHV reactive ionized cluster beam deposition (r-ICBD) system. The base pressure of the system was about $1 \times 10^{-9}$ -9/ Torr and the process pressure $2 \times 10^{-5}$ Torr in oxygen ambience. Glancing X-ray diffraction(GXRD) and in-situ reflection high energy electron diffracton(RHEED) analyses were performed to investigate the crystallinity of the films. The results show phase change from amorphous state to crystalline one with increasingqr acceleration voltage and substrate temperature. It is also found that the phase transformation from $Y_2O_3$(111)//Si(100) to $Y_2O_3$(110)//Si(100) in growing directions takes place between $500^{\circ}C$ and $700^{\circ}C$. Especially as acceleration voltage is increased, preferentially oriented crystallinity was increased. Finally under the condition of above substrate temperature $700^{\circ}C$ and acceleration voltage 5kV, the $Y_2O_3$films are found to be grown epitaxially in direction of $Y_2O_3$(1l0)//Si(100) by observation of transmission electron microscope(TEM). Capacitance-voltage and current-voltage measurements were conducted to characterize Al/$Y_2O_3$/Si MIS structure with varying acceleration voltage and substrate temperature. Deposited $Y_2O_3$ films of thickness of nearly 300$\AA$ show that the breakdown field increases to 7~8MV /cm at the same conditon of epitaxial growing. These results also coincide with XPS spectra which indicate better stoichiometric characteristic in the condition of better crystalline one. After oxidation the breakdown field increases to 13MV /cm because the MIS structure contains interface silicon oxide of about 30$\AA$. In this case the dielectric constant of only $Y_2O_3$ layer is found to be $\in$15.6. These results have demonstrated the potential of using yttrium oxide for future VLSI/ULSI gate insulator applications.

• Journal of the Korean Applied Science and Technology
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• v.27 no.2
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• pp.137-143
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• 2010

Oxide semiconductors Thin-film transistors are an exemplified one owing to its excellent ambient stability and optical transparency. In particular zinc oxide (ZnO) has been reported because It has stability in air, a high electron mobility, transparency and low light sensitivity, compared to any other materials. For this reasons, ZnO TFTs have been studied actively. Furthermore, we expected that would be satisfy the demands of flexible display in new generation. In order to do that, ZnO TFTs must be fabricated that flexible substrate can sustain operating temperature. So, In this paper we have studied low-temperature process of zinc oxide(ZnO) thin-film transistors (TFTs) based on silicon nitride ($SiN_x$)/cross-linked poly-vinylphenol (C-PVP) as gate dielectric. TFTs based on oxide fabricated by Low-temperature process were similar to electrical characteristics in comparison to conventional TFTs. These results were in comparison to device with $SiN_x$/low-temperature C-PVP or $SiN_x$/conventional C-PVP. The ZnO TFTs fabricated by low-temperature process exhibited a field-effect mobility of $0.205\;cm^2/Vs$, a thresholdvoltage of 13.56 V and an on/off ratio of $5.73{\times}10^6$. As a result, We applied experimental for flexible PET substrate and showed that can be used to ZnO TFTs for flexible application.

• Korean Journal of Optics and Photonics
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• v.8 no.1
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• pp.31-36
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• 1997

We measured refractive indices and thicknesses of SiO$_2$ thin films that have been plated on LCD glass substrate for the purpose of preventing the out-diffusion of sodium ions. The best experimental condition to determine refractive index and thickness of SiO$_2$ thin film by using ellipsometry is searched for, where ⅰ) the film thickness is increased uniformly by 20 $\AA$ from 0 $\AA$ to the period thickness while the angle of incidence is fixed and ⅱ) the angle of incidence is increased uniformly by 1$^{\circ}$ from 45$^{\circ}$ to 70$^{\circ}$ while the film thickness is fixed. We estimated the errors in determining the refractive index and thickness by comparing the measurement error of $\Delta$ and Ψ with the calculated one. The ellipsometric constants of SiO$_2$ thin film on LCD glass substrate are measured at several angle of incidence around the Brewster angle, which is the best angle if the experimental error of ellipsometer is not sensitive to the incident angle. Also the best fit refractive index and thickness of SiO$_2$ thin film to these ellipsometric constants measured at several angle of incidenc eas well as the best fit ones to the SE data are obtained using regressional analysis.

• The Journal of Natural Sciences
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• v.8 no.2
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• pp.137-146
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• 1996

To increase the oxidation-resistance of graphite substrate, we have tried to form SiC film on its surface by Sol-Gel method. TEOS(Tetraethyl orthosilicate) and phenol resin have been used as silicon(Si) and carbon(C) sources, respectively. In order to know the effect of the TEOS Sol concentration on the forming of SiC film, we have taken 5 different $H_2O$/TEOS mol ratios of 2, 4, 6, 8 and 10. And the coating states of SiC on the graphite substrate have been analyzed with X-ray diffractometer and scanning electron microscope (SEM), and we have obtained about 5${\mu}m$, 12${\mu}m$, 7${\mu}m$, 7${\mu}m$ and 2 ${\mu}m$ as the thickness of SiC coating layers, respectively. For also knowing the oxidation resistance the SiC coated graphites at $1600^{\circ}C$ were heated again at $1000^{\circ}C$ under air atmosphere for 1 hr, and as a result we have received the weight losses of 26.17%, 20.97%, 17.28%, 21.73% and 28.13%, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.1-10
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• 2018

Recently, there has been rapid development in the field of flexible electronic devices, such as organic light emitting diodes (OLEDs), organic solar cells and flexible sensors. Encapsulation process is added to protect the flexible electronic devices from exposure to oxygen and moisture in the air. Using numerical simulation, we investigated the effects of the encapsulation layer on mechanical stability of the silicon chip, especially the fracture performance of center crack in multi-layer package for various loading condition. The multi-layer package is categorized in two type - a wide chip model in which the chip has a large width and encapsulation layer covers only the chip, and a narrow chip model in which the chip covers both the substrate and the chip with smaller width than the substrate. In the wide chip model where the external load acts directly on the chip, the encapsulation layer with high stiffness enhanced the crack resistance of the film chip as the thickness of the encapsulation layer increased regardless of loading conditions. In contrast, the encapsulation layer with high stiffness reduced the crack resistance of the film chip in the narrow chip model for the case of external tensile strain loading. This is because the external load is transferred to the chip through the encapsulation layer and the small load acts on the chip for the weak encapsulation layer in the narrow chip model. When the bending moment acts on the narrow model, thin encapsulation layer and thick encapsulation layer show the opposite results since the neutral axis is moving toward the chip with a crack and load acting on chip decreases consequently as the thickness of encapsulation layer increases. The present study is expected to provide practical design guidance to enhance the durability and fracture performance of the silicon chip in the multilayer package with encapsulation layer.

• Korean Chemical Engineering Research
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• v.58 no.3
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• pp.369-380
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• 2020

Most mono-crystalline silicon ingots are manufactured by the Czochralski (Cz) process. But If there are oxygen impurities, These Si-ingot tends to show low-efficiency when it is processed to be solar cell substrate. For making single-crystal Si- ingot, We need Czochralski (Cz) process which melts molten Si and then crystallizing it with seed of single-crystal Si. For melts poly Si-chunk and forming of single-crystalline Si-ingot, the heat transfer plays a main role in the structure of Cz-process. In this study to obtain high-quality Si ingot, the Cz-process was modified with the process design. The crystal growth simulation was employed with pulling rate and rotation speed optimization. Studies for modified Cz-process and the corresponding results have been discussed. The results revealed that using crystal growth simulation, we optimized the oxygen concentration of single crystal silicon by the optimal design of the pulling rate, rotation speed and melt charge level of Cz-process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.1-5
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• 2010

We developed a novel micro-electro mechanical systems (MEMS) test socket using silicon on insulator (SOI) substrate with the cantilever array structure. We designed the round shaped cantilevers with the maximum length of $350{\mu}m$, the maximum width of $200{\mu}m$ and the thickness of $10{\mu}m$ for $650{\mu}m$ pitch for 8 mm x 8 mm area and 121 balls square ball grid array (BGA) packages. The MEMS test socket was fabricated by MEMS technology using metal lift off process and deep reactive ion etching (DRIE) silicon etcher and so on. The MEMS test socket has a simple structure, low production cost, fine pitch, high pin count and rapid prototyping. We verified the performances of the MEMS test sockets such as deflection as a function of the applied force, path resistance between the cantilever and the metal pad and the contact resistance. Fabricated cantilever has 1.3 gf (gram force) at $90{\mu}m$ deflection. Total path resistance was less than $17{\Omega}$. The contact resistance was approximately from 0.7 to $0.75{\Omega}$ for all cantilevers. Therefore the test socket is suitable for BGA integrated circuit (IC) packages tests.

• Applied Chemistry for Engineering
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• v.8 no.3
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• pp.395-402
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• 1997

The $SiO_2$ films were prepared by ECR(electron cyclotron resonance) plasma diffusion method, Deal-Grove model and Wolters-Zegers-van Duynhoven model were used to estimate the oxidation rate which was correlated with surface morphology for different orientation of Si(100) and Si(111). It was seen the $SiO_2$ thickness increased linearly with initial oxidation time. But oxidation rate slightly decrease with oxidation time. It was also shown that the oxidation process was controlled by the diffusion of the reactive species through the oxide layer rather than by the reaction rate at the oxide interface. The similar time dependency has been observed for thermal and plasma oxidation of silicon. From D-G model and W-Z model, the oxidation rate of Si(111) was 1.13 times greater than Si(100) because Si(111) had higher diffusion and reaction rate, these models more closely fits the experimental data. The $SiO_2$ surface roughness was found to be uniform at experimental conditions without etching although oxidation rate was increased, and to be nonuniform due to etching at experimental condition with higher microwave power and closer substrate distance.

• Journal of the Korean Vacuum Society
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• v.6 no.3
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• pp.220-226
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• 1997

An optical intensity-type pressure sensor has been fabricated by coupling multimode optical fiber with 100 nm-Au/30 nm-NiCr/150 nm-$Si_3N_4/300 nm-SiO_2/150 nm-Si_3N_4$ optical reflection layer supported by micromachined frame-shape silicon substrate, and its characteristics was investigated. For the application of $Si_3N_4/SiO_2/Si_3N_4$ diaphragm to the optical reflection layer of the sensor, NiCr and Au films were deposited on the backside of the diaphragm by thermal evaporation , respectively, and thus optical low caused by transmission in the reflection layer could be decreased to a few percents. Dielectric diaphragms with uniform thickness were able to be also reproduced because top- and bottom-$Si_3N_4$ layer of the diaphragm could automatically stop silicon anisotropic etching. The respective pressure ranges in which the sensor showed linear optical output power-pressure characteristics were 0~126.64 kPa, 0~79. 98 kPa, and 0~46.66 kPa, and the respective pressure sensitivities of the sensor were about 20.69 nW/kPa, 26.70 nW/kPa, and 39.33 nW/kPa, for the diaphragm sizes of 3$\times$3 $\textrm{mm}^2$, 4$\times$4 $\textrm{mm}^2$, and 5$\times$5 $\textrm{mm}^2$, indicating that the sensitivity increases as diaphragm size increases.

• Journal of the Korean Ceramic Society
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• v.40 no.12
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• pp.1202-1207
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• 2003

Using a recently developed Hybric Plasma-Particle Accelerating Impact Deposition (HP-PAID) process, synthesis of nanostructured silicon coatings has been investigated by injecting vapor-phase TEOS (tetraethosysilane, (C$_2$H$\_$5/O)$_4$Si) into an Ar hybrid plasma. The plasma jet with reactants was expanded through nozzle into a deposition chamber, with the pressure dropping from 700 to 10 torr. Ultrafine particles accelerated in the free jet downstream of the nozzle, deposited by an inertial impaction onto a temperature controlled substrate. By using this process, nanostructured amorphous silicon coatings with grain size smaller than 10 nm could be synthesized. These samples were annealed in an Ar and crystallized at 900$^{\circ}C$ for 30 min. TEM analysis showed that the annealed coatings were also composed of nanoparticles smaller than 10 nm, which showed a good consistency that the average grain size of 7 nm was also estimated from a peak shift of 2.39 cm$\^$-1/ and Full Width at Half Maximum (FWHM) 5.92 cm$\^$-1/ of Raman analysis. The noteworthy is that a strong PL peak at 398 nm was also obtained for this sample, which indicates that the deposited coatings also contained 3∼4 nm nanostructured grains.