• Journal of the Semiconductor & Display Technology
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• v.16 no.3
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• pp.1-7
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• 2017

Multi-wafer planetary type chemical vapor deposition reactors are widely used in thin film growth and suitable for large scale production because of the high degree of growth rate uniformity and process reproducibility. In this study, a two-dimensional model for estimating the effect of the gap between satellite and wafer on the wafer surface temperature distribution is developed and analyzed using computational fluid dynamics technique. The simulation results are compared with the results obtained from an analytical method. The simulation results show that a drop in the temperature is noticed in the center of the wafer, the temperature difference between the center and wafer edges is about $5{\sim}7^{\circ}C$ for all different ranges of the gap, and the temperature of the wafer surface decreases when the size of the gap increases. The simulation results show a good agreement with the analytical ones which is based on one-dimensional heat conduction model.

• Korean Journal of Materials Research
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• v.29 no.11
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• pp.715-719
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• 2019

Molybdenum is a low-resistivity transition metal that can be applied to silicon devices using Si-metal electrode structures and thin film solar cell electrodes. We investigate the deposition of metal Mo thin film by plasma-enhanced atomic layer deposition (PE-ALD). $Mo(CO)_6$ and $H_2$ plasma are used as precursor. $H_2$ plasma is induced between ALD cycles for reduction of $Mo(CO)_6$ and Mo film is deposited on Si substrate at $300^{\circ}C$. Through variation of PE-ALD conditions such as precursor pulse time, plasma pulse time and plasma power, we find that these conditions result in low resistivity. The resistivity is affected by Mo pulse time. We can find the reason through analyzing XPS data according to Mo pulse time. The thickness uniformity is affected by plasma power. The lowest resistivity is $176{\mu}{\Omega}{\cdot}cm$ at $Mo(CO)_6$ pulse time 3s. The thickness uniformity of metal Mo thin film deposited by PE-ALD shows a value of less than 3% below the plasma power of 200 W.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.3
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• pp.264-268
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• 2022

High pressure deuterium (HPD) annealing is an advancing technology for the fabrication of modern semiconductor devices. In this work, gate-enclosed FETs are fabricated on a silicon substrate as test vehicles. After a cycle for the HPD annealing, the device parameters such as threshold voltage (V_TH), subthreshold swing (SS), on-state current (I_ON), off-state current (I_OFF), and gate leakage (I_G) were measured and compared depending on the HPD. The HPD annealing can passivate the dangling bonds at Si-SiO₂ interfaces as well as eliminate the bulk trap in SiO₂. It can be concluded that adding the HPD annealing as a fabrication process is very effective in improving device reliability, performance, and variability.

• Nuclear Engineering and Technology
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• v.54 no.3
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• pp.1024-1029
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• 2022

Composite scintillation screens on a base of Gd_1.2Y_1.8Ga_2.5Al_2.5O₁₂:Ce (GYAGG) scintillator have been evaluated for neutron detection. Besides the powdered scintillator, the composite includes ⁶LiF particles; both are merged with a binder and deposited onto the light-reflecting aluminum substrate. Results obtained demonstrates that screens are suitable for use with a silicon photomultiplier readout to create a prospective solution for a compact and low-cost thermal neutron sensor. Composite GYAGG/⁶LiF scintillation screen shows a pretty matched sensitivity and γ-background rejection with a widely used ZnS/⁶LiF screens however, possesses forty times faster response.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.2
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• pp.163-168
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• 2023

In this paper, a novel platform for chemical sensing and biosensing is presented. The working principle is based on the coupling efficiency and interference properties of optical directional coupler (DC) and multimode interference coupler (MMIC). It has been realized using planar technology to allow integration on a silicon substrate. Firstly, the dispersion curves of DC and MMIC is described, and the design specification of an optimized slot optical waveguide to increase waveguide sensitivity is selected. Next, the sensor response to the refractive index change of sensing analyte is numerically simulated. The numerical results reveal that high effective index change per refractive index unit (RIU) change of analyte is obtained, and the sensitivity can be tuned using the DC and MMIC design technique.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.101-105
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• 2023

Organic photo Diodes (OPDi) give multiple advantages in the growing interest of the flexible optoelectronic devices. Organic semiconductors are freeform as they can deposit on any substrate, so it could be flexible. But the inorganic material photodiodes (PDs) are usually fabricated on silicon wafers which are solid. So, normally PDs are inflexible. By those reasons, we decided to make the vacuum deposited small molecule OPDi. We have investigated the OPDi's J-V characteristic by changing the thickness of p-type layer of OPDi. This device consists of indium-tin-oxide (ITO) / 2,3:6,7-dibenzanthracene (pentacene) / buckminsterfullerene (C60) / aluminum (Al). Its J-V characteristics were measured in the probe station(4156C) that can give dark condition while measuring. And for the luminance characteristics, the photocurrent was measured with the bright halogen lamp and a probe station.

• Korean Journal of Materials Research
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• v.34 no.2
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• pp.105-110
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• 2024

Scanning probe microscopy (SPM) has become an indispensable tool in efforts to develop the next generation of nanoelectronic devices, given its achievable nanometer spatial resolution and highly versatile ability to measure a variety of properties. Recently a new scanning probe microscope was developed to overcome the tip degradation problem of the classic SPM. The main advantage of this new method, called Reverse tip sample (RTS) SPM, is that a single tip can be replaced by a chip containing hundreds to thousands of tips. Generally for use in RTS SPM, pyramid-shaped diamond tips are made by molding on a silicon substrate. Combining RTS SPM with Scanning spreading resistance microscopy (SSRM) using the diamond tip offers the potential to perform 3D profiling of semiconductor materials. However, damage frequently occurs to the completed tips because of the complex manufacturing process. In this work, we design, fabricate, and evaluate an RTS tip chip prototype to simplify the complex manufacturing process, prevent tip damage, and shorten manufacturing time.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.49-60
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• 2010

Semiconductor packages are increasingly moving toward miniaturization, lighter and high performance. Futhermore, packages become thinner. Thin packages will generate serious reliability problems such as warpage, crack and other failures. Reliability problems are mainly caused by the CTE mismatch of various package materials. Therefore, proper selection of the package materials and geometrical optimization is very important for controlling the warpage and the stress of the package. In this study, we investigated the characteristics of the warpage and the stress of several packages currently used in mobile devices such as CABGA, fcSCP, SCSP, and MCP. Warpage and stress distribution are analyzed by the finite element simulation. Key material properties which affect the warpage of package are investigated such as the elastic moduli, CTEs of EMC molding and the substrate. Geometrical effects are also investigated including the thickness or size of EMC molding, silicon die and substrate. The simulation results indicate that the most influential factors on warpage are EMC molding thickness, CTE of EMC, elastic modulus of the substrate. Simulation results show that warpage is the largest for SCSP. In order to reduce the warpage, DOE optimization is performed, and the optimization results show that warpage of SCSP becomes $10{\mu}m$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.5
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• pp.475-480
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• 2017

In this paper, the conductivity of the fine pattern is improved in the insulating substrate by laser-induced forward transfer (LIFT) process. The high laser beam energy generated in conventional laser induced deposition processes induces problems such as low deposition density and oxidation of micro-patterns. These problems were improved by using a polymer coating layer for improved deposition accuracy and conductivity. Chromium and copper were used to deposit micro-patterns on silicon wafers. A multi-pulse laser beam was irradiated on a metal thin film to form a seed layer on an insulating substrate(SiO2) and electroless plating was applied on the seed layer to form a micro-pattern and structure. Irradiating the laser beam with multiple scanning method revealed that the energy of the laser beam improved the deposition density and the surface quality of the deposition layer and that the electric conductivity can be used as the microelectrode pattern. Measuring the resistivity after depositing the microelectrode by using the laser direct drawing method and electroless plating indicated that the resistivity of the microelectrode pattern was $6.4{\Omega}$, the resistance after plating was $2.6{\Omega}$, and the surface texture of the microelectrode pattern was uniformly deposited. Because the surface texture was uniform and densely deposited, the electrical conductivity was improved about three fold.

• Korean Journal of Materials Research
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• v.2 no.3
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• pp.180-190
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• 1992

Some solutions to several major problems in ZMR such as agglomeration of polysilicon, slips and local substrate melting are described. Experiments are performed with varying polysilicon thickness and capping oxide thickness. The aggmeration can be eliminated when nitrogen is introduced at the capping oxide layer-to-polysilicon interface and polysilicon-to-buried oxide layer interface by annealing the SOI samples at $1100^{\circ}$ in $NH_3$ ambient for three hours. The slips and local substrate melting are removed when the back surface of silicon substrate is sandblasted to produce the back surface roughness of about $20{\mu}m$. The subboundary spacing increases with increasing polysilicon thickness and the uniformity of recrystallized SOI film thickness improves with increasing capping oxide thickness, improving the quality of recrystallized SOI film. When the polysilicon thickness is about $1.0{\mu}m$ and the capping oxide thickness is $2.5{\mu}m$, the thickness variation of the recrystallized SOI film is about ${\pm}200{\AA}$ and the subboundary spacing is about $70-120{\mu}m$.