• Tribology and Lubricants
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• 제11권5호
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• pp.20-25
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• 1995

Diamond films were prepared by a hot filament vapor deposition onto polycrystal silicon nitride substrates. Different kinds of silicon nitride containing CaO and $Fe_{2}O_{3}$ were manufactured to investigate the impurity effect of substrate on the morphology of diamond films and their wear behaviors. Nucleation rates and morphologies of diamond films deposited on various kinds of silicon nitride were compared. The highest nucleation rate was observed in a substrate containing 1% of CaO. Wear tests were performed with a silicon nitride ball on the disk geometry to investigate the tribological behavior of diamond film against silicon nitride. This study demonstrated that different morphologies of diamond film due to substrate impurities produced different wear behavior against silicon nitride.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.393-396
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• 1999

A circuit model of silicon substrate coupling for CMOS RF-IC design is developed. Its characteristics are analyzed by using a simple RC mesh model in order to investigate substrate coupling. The coupling effects due to the substrate were characterized with substrate resistivity, oxide thickness, substrate thickness. and physical distance. Thereby the silicon substrate effects are analytically investigated and verified with simulation. The analysis and simulation of the model have excellent agreements with MEDICI(2D device simulator) simulation results.

• Transactions on Electrical and Electronic Materials
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• 제17권4호
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• pp.217-221
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• 2016

In this work, open and short stubs that were fabricated on the silicon substrate and for which the periodically arrayed grounded-strip structure (PAGS) was employed were studied along with their basic RF characteristics for an applicability regarding the RF-matching components. The PAGS-employing open and short stubs showed losses that are much lower than that of the conventional stub on the silicon substrate. Concretely, the Q values of the open and short stubs are 9 and 10.2, respectively, while the Q value of the conventional open stub is 2.5. With the use of the PAGS-employing open and short stubs, a highly miniaturized harmonic-rejection filter was also fabricated on the silicon substrate. The filter exhibited a comparatively sound harmonic-suppression characteristic at n × 13 GHz, and its size is 0.1 mm², which is only 7% of the size of the conventional filter on the silicon substrate.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.871-874
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• 1998

A new transmission line parameter extraction method of iC interconnects on silicon substrate is presented. To extract the acurate parameters, the silicon substrate effects were taken into account. Since the electromagnetic fields under the silicon substrate are propagated with slow wave mode, effective dielectric constant and different ground plane with the multi-layer dielectric structures were employed for inductance and capacitance matrix determination. Then accurate signal transients simulation were performed with HSPICE by using the parameters. It was shown that the simulation resutls has an excellent agreement with TDR/TDT measurements.

• 통합자연과학논문집
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• 제6권3호
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• pp.170-175
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• 2013

Silicon nanowires were detached and obtained from silicon nanowire arrays on silicon substrate using a ultrasono-method. Silicon nanowire arrays on silicon substrate were prepared with an electroless metal assisted etching of p-type silicon. The etching solution was an aqueous HF solution containing silver nitrate. SEM observation shows that well-aligned nanowire arrays perpendicular to the surface of the silicon substrate were produced. After sonication of silicon nanowire array, an individual silicon nanowire was confirmed by FESEM. Optical characteristics of SiNWs were measured by FT-IR spectroscopy. The surface of SiNWs are terminated with hydrogen.

• 한국분말재료학회지
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• 제24권3호
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• pp.248-253
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• 2017

In this study, we investigate the effect of the diffusion barrier and substrate temperature on the length of carbon nanotubes. For synthesizing vertically aligned carbon nanotubes, thermal chemical vapor deposition is used and a substrate with a catalytic layer and a buffer layer is prepared using an e-beam evaporator. The length of the carbon nanotubes synthesized on the catalytic layer/diffusion barrier on the silicon substrate is longer than that without a diffusion barrier because the diffusion barrier prevents generation of silicon carbide from the diffusion of carbon atoms into the silicon substrate. The deposition temperature of the catalyst and alumina are varied from room temperature to $150^{\circ}C$, $200^{\circ}C$, and $250^{\circ}C$. On increasing the substrate temperature on depositing the buffer layer on the silicon substrate, shorter carbon nanotubes are obtained owing to the increased bonding force between the buffer layer and silicon substrate. The reason why different lengths of carbon nanotubes are obtained is that the higher bonding force between the buffer layer and the substrate layer prevents uniformity of catalytic islands for synthesizing carbon nanotubes.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.611-611
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• 2013

In this study, iron oxide nanoclusters layer (Nc) was prepared onto functionalized silicon substrate by wet method. The amine-terminated SAM fabricated on silicon substrate (APTMS/Si) was carried out by UV-treatment and immersed into the FeCl3/HCl aqueous solution. Then, Nc were immobilized onto oxidized SAM silicon substrate (SAMs/Si) through electrostatic interaction between cationic Nc and anionic SAMs/Si. This catalytic layer (Nc/SAMs/Si) was used to grow carbon nanotubes (CNTs). The characterization results clearly show that the well-graphitized CNTs were synthesized by using functionalized silicon substrate as a template having appropriate density of catalyst. These consequences show that SAM containing template is important to achieve the effective layer of catalyst to synthesize CNTs.

• Transactions on Electrical and Electronic Materials
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• 제17권2호
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• pp.118-120
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• 2016

A coplanar waveguide employing periodic 3D coupling structures (CWP3DCS) was developed for application in miniaturized on-chip passive components on silicon radio frequency integrated circuits (RFIC). The CWP3DCS showed the shortest wavelength of all silicon-based transmission line structures that have been reported to date. Using CWP3DCS, a highly miniaturized impedance transformer was fabricated on silicon substrate, and the resulting device showed good RF performance in a broad band from 4.6 GHz to 28.6 GHz. The device as was 0.04 mm² in size, which is only 0.74% of the size of the conventional transformer on silicon substrate.

• 한국결정학회지
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• 제12권3호
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• pp.166-170
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• 2001

실리콘 기판에 도핑되어 있는 도판트는 종류에 따라 코발트와 실리콘 기판과의 반응에 영향을 준다. 인은 붕소나 비소에 비해 코발트와 실리콘과의 반응을 억제하여 저온 열처리 동안에 CoSi₂대신에 CoSi가 형성되도록 한다. CoSi층 내에서의 확산원소는 Si으로, CoSi 층은 Co/CoSi 계면에서 성장하며 반응에 참여하는Si 소모에 의해 생기는 기판의 빈 공간을 태우기 위해 Si 기판쪽으로 이동한다. 게이트 측벽에서는 접촉되어 있는 게이트 산화막과의 결합에 의해 CoSi층의 이동이 억제된다. 따라서 기판의 빈 공간을 태우지 못하게 되어 게이트 측벽 아래에 기공이 형성된다.

• 대한전자공학회논문지SD
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• 제38권11호
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• pp.781-790
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• 2001

실리콘 웨이퍼 두께에 따른 PZT 박막 적외선 감지소자의 성능변화를 이론적 해석 및 실험적 검증을 통하여 분석하였다. 실리콘이 모두 식각되었을 때 최대값을 보이는 전류응답도는 소자의 뒷면에 남아있는 실리콘의 두께가 50㎛로 두꺼워질 때까지 기하급수적으로 줄어들다가, 그 이상의 두께에서는 전류응답도의 감소폭이 현저히 줄어들었다. 실리콘이 모두 식각된 적외선 감지소자는 450㎛두께의 실리콘이 남아있는 소자에 비해 100배 이상의 높은 전류응답도를 보였다. 이러한 이론적인 해석을 검증하기 위하여 실리콘 기판미세가공법을 이용하여 세 가지 다른 실리콘 두께를 가진 적외선 감지소자를 제작하였다. 제작한 소자에서 측정한 전류응답도의 변화는 이론적 해석값과 좋은 일치를 보였다. 한편, 실험을 통하여 실리콘 두께가 소자의 전류응답도 뿐만 아니라 응답속도에도 큰 영향을 준다는 것을 확인하였다.